SU1591025A1

SU1591025A1 - DEVICE FOR MANAGING THE SAMPLE OF MEMORY BLOCKS

Info

Publication number: SU1591025A1
Application number: SU884603357A
Authority: SU
Inventors: Igor B Bozhenko; Oleg K Meshkov; Aleksandr G Krot
Original assignee: Lvovskij Polt Inst
Priority date: 1988-11-09
Filing date: 1988-11-09
Publication date: 1990-09-07

Description

The invention relates to the field

computing technology and can be used in memory systems that use the reconfiguration of the failed elements. The aim of the invention is to increase reliability. The device contains a group of two-position switches 1, counters 2, 3, decoder 4, switch 5, group of registers 6, group of comparison circuits 7, register 8, outputs 9 of selection of memory blocks of the group, address input 10, input 11 of initial installation and synchronous input 1 2 of the device . The goal is achieved by the introduction of new elements and links. 2 Il.

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The invention relates to computing and can be used ₍ called in memory systems that use the reconfiguration of failed elements.

The aim of the invention is to increase reliability.

Figure 1 shows the functional diagram of the device; figure 2 - timing diagram of the device.

The device contains a group of two-position switches G, counters 2 and 3, a decoder 4, a switch 5, a group of registers 6, a group of comparison circuits 7, a register 8, exits 9, sampling of memory blocks of a group, an address input 10 of the device, an input

11 initial installation and synchronous input

12 devices.

In Fig. 2, the following designations are used: a — SI synchro pulses, arriving at the device sync-input 12, b — low-order output of counter 2, c — counter 2 overflow output, g-e — first, second, and last decoder 4, respectively; and - first, second and last outputs of register 8, respectively, k - switch 5 output, l - low-order output of counter 3, м-о - respectively, the states of the first, second and last of registers 6, n - receipt of addresses of memory blocks at input 10 devices, p - signals at the outputs, 9 devices.

The device works as follows.

Disabling memory blocks is set by setting the corresponding switches 1 to the state "0". The input 12 to the counter 2 receives the clock (Fig.2A), in which the counter

• modified (Fig.26). The signal overflow counter (figv) with. the state of the switches is entered in the register 8 (fig.2zh-i), and the counter 3 is reset. According to the state of counter 2, switch 5 performs a sequential polling of the state of the output bits of register 8, while counter 2 is modified by a positive

. the front of the sync pulse, and the next 7 digit of the register 8 is connected to the counting input of the counter 3 at the level “O” of the sync pulse, and at the level “1” of the sync pulse, the output of the switch

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blocked (fig.2k). Thus, the counter 3 is incremented once again at the level "1" of the next digit of the register 8 (Fig.2l).

At the same time, according to the state of the counter 2, the decoder 4 generates recording pulses into the registers 6 of the current state of the counter 3 corresponding to each switch (Fig. 2d-e). The initial setting of registers 6 is set by the signal at input 11. The state "0" of bits of register 8 blocks the entry in the corresponding registers

6. So in the registers corresponding to the included memory blocks, the addresses assigned to these blocks are entered sequentially, starting with the address "1" (fig.2m-o). In case all the memory blocks are on, the last of these blocks is assigned the address "0"

(Fig.2o).

At the end of the polling, the counter 2 generates an overflow signal and the state of the switches 1, which can be changed during the polling, is again entered into the register 8. Then the addressing of the included memory blocks begins again.

Input 10 to the device synchronously to the signals from the synchronous input 12 receives the addresses of the selected blocks (fig.2p).

When the incoming address code coincides with the conditional address code on one of the registers 6 and the level "0" of the clock signal from input 12 from the output of the corresponding circuit 7 (output 9) receives a sampling signal (fig.2r) of the memory block.

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Claims

A device for managing a sample of memory blocks, containing two from a meter, a decoder, a switch, a group of registers and a group of comparison circuits, the output of the K th group comparison circuit being connected to the K th output of a sample of memory blocks of the group (K =

= 1, ..., 14), where M is the number of served memory blocks), the device’s address input is connected to the first information input of the K th group comparison circuit, the second information input of which is connected to the output of the K-th group register, the installation input in "0" and informational input of which is connected respectively to the input of the initial installation of the device and

to the output of the first counter, sync

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which is connected to the output of the switch, whose address input is connected to the output of the second counter and to the input of the decoder, the device's synchronous input is connected to the synchronous input of the second counter, characterized in that, in order to improve reliability, a register is entered into it, connected to the input of the sign of readiness for the operation of the corresponding block of the device's memory, the K-th digit of the register output is connected to 1025 "

directly to the K-th information input of the switch, the input resolution of the recording of the K-th group register and the first building input of the K-th group comparison circuit, the K-th output of the decoder is connected to the synchronous input of the K-th group register, the overflow output of the second counter is connected to the synchronous input of the register and to the input of the installation in the “O” of the first counter, the synchronous input of the device is connected to the gate input of the switch and to the second gate inputs of the group comparison circuits.

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