SU1348840A1 - Program debugging device - Google Patents

Description

Minimal internal language of the computer being designed. The aim of the invention is to expand the functionality by memorizing the start command, the end command address, the number of repetitions of the cycle, and the cycle time. The device contains the block 1 of the buffer memory, the block 2 of the associative memory, the register 3 of the key, the protection circuit, the register 4 of the command code.

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The invention relates to computing, in particular, to devices for recording the results of program tests in digital data processing systems.

The aim of the invention is to extend the functionality by storing the start command, the address of the start command of the number of repetitions of the cycle, and the cycle time.

Yah FIG. 1 shows a block diagram of the device; in fig. 2 is a block buffer circuit diagram; in fig. 3 is a block diagram of an associative memory unit.

The device for debugging programs contains (Fig. 1) block 1 of buffer memory (PSU), block 2 of associative memory, register 3 of the protection key, register 4gfcoAa commands, register 5 of the command address, groups 6-8, elements counter 9 of the address , decoder 10 commands, comparison circuits 11 and 12, element AND 13, elements OR 14-16, delay elements 17-19, groups 20 - 23 information inputs of the device, control inputs 24 and 25 of the device, group 26 of information outputs of the device, outputs 27-29 devices.

The buffer memory unit 1 contains (Fig. 2) groups 30 and 31 of information inputs, a group of 32 address inputs, inputs 33-36 of a block, a group of 37 information outputs, an output 38, a decoder 39 of the address, an AND 40 element, a group of 41 SHS and N memory cells (N is the number of cycles recorded by the device), each of which includes a register of 42 cycles, a counter of 43 cycles, a counter of 44 times, circuits 45 - 47 comparisons, groups 48840

register 5 command addresses, groups of elements AND 6, 7 and 8, address scanner 9, 10 commands decoder, comparison circuits 11 and 12, AND element 13, OR elements 14, 15 and 16, delay elements 17, 18 and 19. The device provides fixing in memory the number of cycles executed, the code of the command to start the cycle and its execution time. 1 3.p. f-ly, 3 ill.

Py 48 and 49 elements And elements And 50 53, element ШШ 54 and trigger 55,

Unit 2 associate Eva memory contains (FIG. 3) inputs 56 and 57 of the block, group 58 of information inputs input 59 of the block, output 60, the element ILI– NOT 61, the element I 62 and M cells (M is the maximum allowable number of nested in other program modules), each of which includes a return address counter 63, a comparison circuit 64, a group of AND elements, an AND element, 66 trigger 67 and a delay element 68.

The device works as follows.

In the initial state, registers 4 and 5, the address counter 9, and in each storage cell of the BP unit 1 - re-1-ister 42, counters 43 and 44 and trigger 55, and in each cell of the PV block 2 - counter 63 and trigger 67 are in the zero state.

Before starting work on the group of 20 device inputs, the protection key code of the analyzed program is written into the protection key register 3, the cycle parameters of which are recorded in the PD. The device is ready for operation.

When the device operates in the first mode, the group 21 of the device's inputs from the computer program state word register to the first group of information inputs of the comparison circuit 12 receives the key code of the executed program, a high potential signal from the output of the comparison circuit 12 is fed to the enabling inputs of group 6 AND elements and AND 13 elements as long as the code value of the protection key of the program being executed is equal to the code value received from register31348840

pa 3 protection keys for the second group of information inputs of the comparison circuit 12.

The codes of the commands of the program being analyzed (according to the group of 22 inputs of the device, the codes of the commands executed by the computer are received) through the group of 6 elements I arrive at the first input of the group 7; the control is not the return address (and at the beginning of work it will be), then 6A, the comparison of each cell of block 2 is low potential (the situation of mismatch of codes at the inputs of the comparison circuit), and the output of the LII-HP 61 element is high (permitting AND and a group of information inputs), supplied to the first

doses of the decoder 10 teams. The command addresses on the group of 23 inputs of the device arrive at the first input of the group of 8 elements I, the first group of information inputs of the comparison circuit 11, the group 58 of the inputs of block 2, the corresponding EI inputs of the group 30 of information inputs of the PSU and the group 31 of information inputs of the PSU.

If the next command is a command of conditional or unconditional transfer of control, then, respectively, from the first or second output of the decoder 10 commands a pulse is issued.

input element H 62. This signal is received through the second input 57, element AND 62, output 60, input 33 BP to control the input of all circuits 45 comparing the BP,

In case none of the cycle register 42 contains a code (supplied to the second group of information inputs of the respective comparison circuits 45) equal to the code currently received on the first group of information inputs of the comparison circuits 45 (consists of the control command transfer code code address end cyc

the signal that is through the element PLI 14 25 d j code of the address of the beginning of the cycle), then

enters the enable inputs of groups 7 and 8 of the AND elements, with the result that the command code is recorded in register 4 of the command code, and the addresses of this command are recorded in register 5 of the command address. The code from register 4 goes to the corresponding inputs of group 30 of information inputs of the PSU, and the code from register 5 goes to the corresponding inputs of group 30 of inputs of the PSU and to the second group of information inputs of the comparison circuit 11, which has a low potential at the control input at the output . The signal that appeared on the first or second output of the decoder 10, respectively, the delay element 18 or the delay element 19 and the IL element 16 is fed to the control input of the comparison circuit 1 1 at the moment when the command address code appears on the device input group 23 that is currently being managed. If the code arriving at the second group of information inputs is greater than the code arriving at the first group of information inputs (recognizing the presence of a cycle), then the comparison circuit 11 produces a pulse signal by the signal at the control input, a sign of the detection of the cycle. In this case, if in block 2 there was not previously recorded a single transfer of control with a return or the current address of the transfer

control is not a return address (and at the beginning of work it will be), then the output of the mismatch of the comparison circuit 6A of each cell of block 2 is low (the mismatch situation of the codes at the inputs of the comparison circuit), and the output of the ILN-HP 61 is high (I allow the input of the element H 62. This signal comes through the second input 57, element 62, output 60, input 33 BP to the control input of all circuits 45 comparison BP,

In case none of the cycle register 42 contains a code (enters the second group of information inputs of the respective comparison circuits 45) equal to the code currently being transmitted to the first group of information inputs of the comparison circuits 45 (consists of the control command transfer code, code addresses of the end j code of the address of the beginning of the cycle

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When a signal arrives at the control, all the comparison circuits 45 produce a signal at the first output (this will be the case at the beginning of the operation). These signals are fed to the corresponding inputs of the element AND 40 BP, the output of which then forms a signal. (entry signal), arriving at the output of the PSU 38 and the second input of the group of 48 elements AND of each cell. The entry signal provides entry of the cycle code (control command code, cycle end address code, cycle start address code) into the corresponding 0 bits of the cycle register 42 of the corresponding BP cell whose address is determined by the resolving potential on the corresponding number of this BP cell of the decoder 39 output. addresses (at the beginning of work it is the first cell).

After entering the cycle code into the register 42 of the corresponding BP cell, the second group of information outputs of this register is fed to the second group of information inputs of the circuit 47 comparing this cell, and the code of the address of the end of the cycle comes from the third group of information outputs of this register to the second 1 information input of the circuit 45 This cell receives the address code of the beginning of this cycle. For the first groups of information inputs of circuits 46 and 47, comparisons of each 1 school with group 5

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At 31 inputs, the power unit receives the address code of the current program command.

The comparison circuit 46 of each BP cell provides the output potential from the output, if this code is greater, and the 47 comparison circuit of each BP cell, if it is less than the code values supplied to their second groups of information inputs. These permitting potentials provide the formation of the permitting potential at the output of the corresponding element AND 50, which is fed to the second inputs of the elements AND 52 and 53 of the corresponding cell BP and through the corresponding element OR 54 to the second input of the corresponding element AND 51, thereby allowing the input of counting pulses to A computer (via the control input 24 of the device, the input 35 of the PSU and the open element I 51) to the counting input of the corresponding time counter 44, in which the code corresponding to the total realization time yes is generated this cycle.

The signal from the output of the PSU 38 through the delay element 17 and the element OR 15 enters the counting input of the scheduling address 9, increasing its content by one. The code from the group of outputs of the counter 9 through the group 32 of the address inputs of the PSU enters the input of the decoder 39, at the corresponding output of which a resolving potential appears that ensures the recording of information into the next BP cell when the described situation occurs.

If in the loop register 42 of one of the BP cells there is stored a code equal to the loop code currently being transmitted to the first group of information inputs of the comparison circuit 45 of all the BP cells, then when a signal arrives at the control input, a signal is output from its second output I go to the counting input of the corresponding cycle counter 43 and increment; its content is one (the counter contains the number of realizations of the cycle, reduced by one, the zero code of this counter with a nonzero code value of the corresponding cycle register 42 After completion of the operation of the device in the first mode degeneracy indicates allocation / dennogo, once implemented cycle).

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In the event that the code (address of the current command), which enters the group of PSU inputs 31 to the first groups of information inputs of the comparison circuits 46 and 47 of each cell, does not satisfy the described conditions for issuing resolution potentials from the output of these circuits (which corresponds to the exit from the cycle, fixed in this cell), then the inhibitory potential from the output of the element And 50 of the corresponding cell (in the absence of a resolving potential at a single output

5 of the corresponding trigger 55) prohibits the arrival of counting pulses at the input of the corresponding time counter 44.

In the process of executing the analyzed program, it is possible to transfer control to another part of the program (module) on the command of unconditional transfer of control with return. If such a situation arises during the implementation of the cycle, then the execution time of the commands of the module to which control is transferred must be taken into account in the total cycle implementation time. Therefore, if the next command of the program being analyzed is an unconditional control transfer command with the return that a pulse signal is output from the third output of the command decoder 10, which is fed to BP unit 36 (BP operation in this case is described below) and input 59. In this case, block 2 works as follows.

The signal from input 59 through the open cell AND 66 of the corresponding cell (initially the first) sets the corresponding trigger 67 to the one state and enters the second inputs of the elements.

5 groups 65 of the given cell (high potential at the single output of the trigger 67 of this cell opens the element And 66 of the subsequent cell), This signal ensures that the code is entered

The Q addresses of the unconditional transfer control command return to the counter 63 of the return address. This signal, after passing through the corresponding delay element 68, reaches the counting input of the corresponding return address counter 63 and increases its content by one, thereby forming the return address value in the counter.

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the calling part (module) of the program from the called one. The code from the output group of the counter 63 of the return address of each cell arrives at the second group of information inputs of the respective comparison circuits 64, the first groups of information inputs of which receive the value of the current address of the program being executed from the group 58 of information inputs.

When a signal arrives from the third output of the descrambler 10 commands to the input 36 of the PSU, the block 1 of the buffer memory works as follows. This signal is fed to the first input element And 53 of each cell. At the output of the 53 And BP cells having the resolving potentials at the second input (for the cells in which the total time of realization of the corresponding cycles is counted), a trigger 55 signal is generated to set the corresponding cells to one, which ensures the presence of the resolving potential at the output of the corresponding element OR 54. As a result, the cumulative time of the implementation of this cycle is calculated despite the appearance of a sign of the end of the cycle after the execution of the unconditional transfer control command and with the return. The return from the called part of the program (module) to the caller is carried out by an unconditional command to transfer control, with the pulse signal from the second output of the decoder 10 commands through delay element 19 and input 56 to the control inputs of the comparison circuits 64. A pulse signal appears at the second output only of the cell comparison circuit 64, for which the codes being compared at a given time are equal (i.e. control is transferred to the address recorded in the counter 63 of the cell's return address). The corresponding trigger 67 is reset by this signal. At this point in time (if the codes are equal), the first output of the comparison circuit 64 will be high, and the output of the OR-NOT 61 element will be low (prohibiting), which prohibits the loop signal from passing through the 62 elements. to the power supply unit (the return from one module to another will not be perceived as a sign of the cycle).

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The signal generated from the second output of the decoder 10 commands through the delay element 19 is also fed to the input 34 of the PSU, while the BP works as follows. This signal goes to the element And 52 of each cell.

but flushes trigger 55 only

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those BP cells for which the current address of the transfer control is within their respective cycles, i.e. in which the total time is calculated.

After deciphering the command end

5, the operation of the analyzed program pulse signal from the fourth output of the decoder 10 commands resets the contents of the counter 9 of the address and sigQ on the control output 27 of the device sig the computer about the end of operation of the device in the first mode. In case, when operating in the first mode, the number of cycles detected in the program exceeds the capacity

5, the overflow signal from the output of the address 9 through the element And 13 is outputted via the control output 28 of the device in the computer, signaling an emergency situation. When the device is operating in the second mode, the control input 25 of the device through the element OR 15 from the computer sends the output signals to the counting input of the address counter 9, each of which is output after reading the contents of the next BP cell from the group 26 of the device's information outputs. Depending on the code located on the counter 9 addresses, the corresponding output bus of the address decoder 39 is excited, connected to the permissive input of the group 49 of the elements AND of the corresponding cell. This ensures alternately (from 1 to N) transferring the contents of register 42, counter 43, counter 44 of the time of the next BP cell through group 41 of the OR elements to group 37 of the information outputs of the BP and then to group 26 of the information outputs of the device.

The output signal is fed to the counting input of the counter 9 address until the signal of its overflow is given to the control output 29 of the device, signaling the end of operation of the device in the second mode.

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Claims (2)

1. Device for debugging programs containing a block of buffer memory, command address register, address counter, first AND group, first OR element and first delay, buffer memory block contains an address decoder, AND element, OR group and N storage elements cells, where N is the maximum number of cycles of the program under study, and each memory cell contains the first comparison circuit, cycle register, cycle counter, first and second groups of elements AND, the first group of information inputs of the device connected to the first inputs of elements AND of the first group, the outputs of which are connected to the group of information inputs of the command address register, the group of outputs of the command address register are connected to the corresponding inputs of the first comparative number of the first comparison circuit of each storage cell of the buffer memory block, the outputs of the OR elements of the buffer memory block ow The group of information outputs of the device, the output of the AND block of the buffer memory are connected through the first delay element to the first input of the first OR element, the output of which It is connected to the counting input of the address counter, a group of information outputs of the address counter is connected to a group of inputs of the address decoder of the buffer memory block, the read input of the device is connected to the second input of the first ELF element, the i-th output of the decoder of the buffer memory block address (1 1, p) is connected to the first inputs of elements AND of the first and second groups of the i-th storage cell of the buffer memory block, outputs of the AND elements of the second group of the i-th memory cell of the buffer memory block are connected to the i-th inputs of the OR block elements of the buffer memory TI, the output of the inequality of the first comparison circuit of the i-th storage cell of the buffer memory block is connected to the i-th input of the AND block of the buffer memory, the second inputs of the AND elements of the first group of each storage cell of the buffer memory block are connected to the output of the AND block of the bu1 memory block memory memory, group of information outputs of the register 48840 the command addresses are connected to the third inputs of the corresponding elements AND of the first group of all the storage cells of the buffer memory block, the outputs of the AND elements of the first group of the i-th memory cell are connected to the information inputs of the cycle register of the i-th memory cell, information 10 outputs of the cycle register of the i-th storage cell are connected to the inputs of the second compared number of the first comparison circuit of the i-th memory cell, information outputs of the cycle register and 15 cycles counters of the i-th memory cell are connected to the second inputs of the corresponding elements AND of the second group, characterized in that, in order to expand the functional possibilities by memorizing the start command, the start command address, the end command address, the number of repetitions of the cycle and the cycle time , the program key registry key is entered into the device, the command code register, the first and second comparison schemes, the second and third groups of AND elements, the second and third OR elements, the second and third elements of the 3Q support, decryption or commands, an And element and an associative memory block, a time counter, a second and a third comparison circuit, four AND elements, an OR element and a trigger, the second group of information inputs of the device are connected to the first inputs of elements in each memorized cell of the buffer memory block. And the second group, the outputs of which are connected to the first inputs of the elements of the third group and the inputs of the command decoder, the outputs of the elements of the third group are connected to the information inputs of the command code register, you-. the strokes of which are connected to the third inputs of the corresponding elements AND of the first group and the corresponding inputs of the first compared number of the first comparison circuit of all storage cells of the buffer memory block, the third and fourth groups of information inputs of the device are connected cd- responsibly with the x group of the inputs of the first compared number G1 of the first comparison circuit the group of information inputs of the security key register, the output of which is connected to the input of the second compared number of the first comparison circuit, the output of the comparison of the first circuit 35 50 one the comparison is connected to the first input of the And element and to the second inputs of the AND elements of the second group, the output of the AND element is the output of the device error, the first group of information inputs of the device is connected to the group of information inputs of the associative memory unit, with the group of inputs of the first compared number of the second comparison circuit, with the group of inputs of the first comparable number of the second and third comparison circuits, all the storage cells of the buffer memory block and with the third inputs of the corresponding AND elements of the first group and the corresponding The first, second, third, and fourth outputs of the instruction decoder are connected to the first input of the second OR element, to the second input of the second OR element, to the reverse input of the associative memory, and with the stop output of the device, the first, second, third and fourth outputs of the command decoder are connected respectively via the second delay element to the first input of the third OR element, through the third delay element - with the second input of the third element OR, with the first input of the first element AND of all storage cells of the buffer memory block and with the input of zeroing the address counter, the output of the third delay element is connected to the clock input of the associative memory block and with the first input of the second element AND of all storage cells the buffer memory block, the output of the second element OR is connected to the second inputs of the AND elements of the first and third groups, the output of the third element OR is connected to the clock input of the second comparison circuit, the equality output of which is connected to the input By reading the associative memory block readout, the output of which flag is connected to the clock input of the first comparison circuit of all storage cells of the buffer memory block, the device’s timestamp input is connected to the first input of the third element And all memory cells of the buffer memory block, the address counter overflow output is connected to the second input of the element AND is the output of the end of reading the device, the group 88840 2 the team’s address register register output is connected to the input group of the second compared number of the second comparison circuit, the equality output of the first comparison circuit of the i-th memory cell is connected to the counting input of the cycle counter of the i-th memory cell of the buffer memory block, outputs 0 code of the address of the end of the cycle and the beginning of the cycle of the register of the i-th memory cell are connected to the inputs of the second compared number of the second and third comparison circuits of the i-th respectively 15 of the storage cell, the outputs are Less and More than the second and third comparison circuits of the i-th memory cell are connected respectively with the first and second inputs of the fourth element And 20 i-th storage cell, the output of which is connected to the second inputs of the first and second elements And and the first input of the i-th storage cell, the outputs of the first and second elements And 25 of the i-th storage cell are connected respectively to the inputs of the zero setting and the trigger unit of the i-th storage cell, the direct output of which is connected to the second input of the OR element 30 storage cells, the output of which is connected to the second input of the third element And the i-th storage cell, the output of which is connected to the counting input of the time counter of the i-th storage cell, the outputs of the time counter of the i-th memory cell connected to the second inputs of the corresponding elements And the second group i-th memory cell. Q 2. The device according to claim 1, characterized in that the block of associative memory contains an element OR NOT, M elements AND (M is the maximum allowable number of embedded program modules .g), M triggers, M delay elements, M return address counters, Mgroup elements AND, M comparison circuits, (M + 1) -th element AND, the group of information inputs of the block is connected to the first inputs of elements AND of all groups and the group of inputs of the first compared number of all comparison circuits, the clock input of the block is connected to clock inputs of all circuits comparison. 50 55 the output of the K-th counter of the return address (K Y / Y) is connected to the input of the second comparable number of the K-th comparison circuit, the outputs are Equal and Not equal to the K-th  3134 Comparison circuits are connected respectively to the input of the installation of a zero K-th TRI1ter and to the K-input of an OR-NOT element, the output of which is connected to the first input of (M + 1) -th element AND, the read input of the block is connected to the second input (M + 1) th element of AND, the output of which is the output of the feature of the block, the input of the access of the block is connected to the first, the first inputs of the first M elements And, the inverse output of the first trigger soy M 0 dinene with the second input of the first element I, the unit output Ki o of the trigger is connected to the second input (Ktl) -ro of the element I, the output of the K-r-o element I is connected to the single input of the K-th trigger, with the second inputs of the elements I K-th group and through the K-th delay element with the counting input of the K-th counter return address, the outputs of the elements And K group are connected to the information inputs of the counter return address. FIG. 2 56 S6 go fie. 3 Compiled by I.Sigalov Editor E.Kopcha Tehred A.Kravchuk Proofreader A.Obruchar Order 4803/49 Circulation 670 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4