SU1397908A1 - Microprogram control device - Google Patents

Abstract

The invention relates to automation and computer engineering and can be used in computer and microprogrammed computer systems. The invention is intended to expand the field of application of the device by ensuring that the device operates in priority interrupt mode. The device contains a block of 1 memory of microprograms, a register of 2 addresses, a register of 3 micro-operations, a multiplexer of 4 addresses, a register of 5 return, a multiplexer 6 of logical conditions, the first 7 and second 8 of the comparison circuit, the first 9 and second 10 elements of OR, the first 11 and second 12 elements And, trigger 13 start, generator 14 clock pulses, one-shot 15. 3 Il. with S (L with so about about 00

Description

The invention relates to automation and computing and can be used in computer and microprogrammed computer systems.

The aim of the invention is to expand the field of application of the device by ensuring that the device operates in the interrupt mode by priority.

Figure 1 shows the functional diagram of the firmware control device; Fig. 2 is a time chart of the operation of the device in the interrupt mode; FIG. 3 shows a device operation algorithm.

The microprogram control unit contains block 1 of microprogram memory, field 1, micro-operations of microprogram memory block, field 1, microprogram memory block addresses, microprogram memory block logic condition code Ij, low-order output of microprogram memory block address, field 1 firmware memory priority code, firmware memory command end field 1, address register 2, micro-operation register 3, address multiplexer 4, return register 5, logical conditions multiplexer 6, first 7 and second 8 comparison circuits The first 9 and second 10 elements OR, the first 11 and second 12 elements AND, trigger 13 start, generator 14 clocks, first 14, and second 14 outputs of the generator 14 clocks, one-shot 15-, output 16 micro-operations of the device, start 17 device, the second information input 18 of the multiplexer, the inputs of the address 19 and priority 19 of the input 19 of the operation code of the device, the third information input 20 of the multiplexer 4 addresses, the input 21 of the code of logical conditions of the device, the first 22 and the third 23 information inputs of the multiplexer 6 logical conditions, output 24 of article rshego discharge floor C address block memory microprograms.

The device works as follows.

The change of operation codes at the input 19 of the device occurs between the pulse

yourself

and

H

carried out taking into account the signals QC (field 1 of block 1) and PR (output of the comparison circuit 8) (the outputs of the generator 14 of the comparison circuit 8 and Q

five

0 5

0

five

l 1 block 1 as the external outputs of the device conventionally not shown) ..

In the initial state, all elements of the device memory are in the zero state. In field 1, the zero cell of block 1 is written 1.

A single signal from the output of this field through the element OR 10 is fed to the first control input of the multiplexer 4 address, at its second control input there is no single signal, therefore the multiplexer 4 address, according to the algorithm of its work, passes the address code to the information input of the register 2 address operation input 19, the address code input 19 operation code device.

In the operation mode without implementing interrupts on the signal. Start from input 17 of device trigger start 13 is set to one and turns on generator 14. On the falling edge / first clock pulse G, from vygheda 14, generator 14, the register 2 address is inserted into the address 2 the address of the first microcommand of the first firmware. This address is then fed to the input of block 1. As a result, the micro-operations code appears at the output of its field 1, the address of the next microcommand appears at the output of field 1, the output of the field C (if it is a branch macro instruction) is the code of the logical condition being checked floor 1 is the low-order bit of the address of the next microcommand (if this microcommand is linear), on you

During lol 1, the priority code of the next microinstruction. The signal from the output of field 1 of block 1 in all microinstructions of the microprogram, except the last one, is equal to zero.

On the trailing edge of the clock pulse t from the output 14 of the generator of 14 clock pulses, the operation code is written into the register 3 of the microoperations and then goes to the output of the microoperations of the :: trio.

If the read micro-command contains r in the field of logical conditions a null code, then the multiplexer 6 of logical conditions passes on its output the value of the signal from the output of the field 1 low-order bit of the address of memory block 1.

If the microcommand of branching is read, by the code of logical conditions

from the field 1j of block 1, the multiplexer 6 of logical conditions passes to its output as the value of the least significant bit of the address the value of the checked logical condition. Thus, the modification of the lower address bit is performed.

Since the exit floor 1 end

the command signal is already zero, then the multiplexer 4 of the address passes to the output and then to the information input of the register 2 addresses from its first information input the address of the next microcommand from the outputs field 1 of unit 1 and multiplexer 6 of logical conditions.

At the inverse control input of the comparison circuit 8, there is a zero enable signal from the output of the element OR 9, since the return register 5 is in the zero state. At the control input of the comparison circuit 7, there is no enable signal.

In the end field 1g of the command of block 1, the format of the last microcommand of the microprogram is recorded as one. The QC signal coming through the element OR 10 to the first control input controls the operation

HOBOPI code of the received operation. The PR signal is also fed to the control input of the return register 5, allowing the address and priority codes of the next microcommand of the interrupted microprogram to be written to it from the corresponding outputs of block 1. Recording occurs on the falling edge of the tact

14

I

f pulse from the second generator output 14 clock pulses. Only after this, the new clock pulse, from the first output 14, of the generator 14, with its falling edge, allows writing into the register 2 of the address of the address code of the booty firmware. With the recording of information in the register 5 return element OR 9 forms a single signal PB. This signal, acting on the inverse control input of the comparison circuit 8, blocks its operation, thus prohibiting the secondary interruption, until the first one is executed. The signal RV is also fed to the input 23 of the multiplexer 6 logical conditions. The device then executes the interrupt firmware in the same way as the previously interrupted firmware. The interrupt firmware can use

multiplexer 4, which, with incoming 30 working firmware, consisting of

This signal passes to its output and further to the input of register 2 addresses the address code of the new operation.

Further, the cycle of operation of the device in the non-interrupted mode is repeated. In the interrupt mode, the device works only when a new operation, the address code of which goes to address input 19, input 19 of the operation operation code, has a higher priority than the current microcommand of the firmware being executed.

Since at the inverse control input of the comparison circuit 8 there is a resolving zero signal with the arrival at the input A of the comparison circuit 8 of the priority code higher than the priority code of the next microcommand of the current microprogram, which enters the input of the circuit B, the output of the comparison circuit 8 appears PR signal It goes through the element OR 10 to the first control input of the multiplexer 4 addresses (there is no single signal at the second control input).

The multiplexer 4 addresses passes to the input of the register 2 addresses address

five

0

microinstructions, lower priority firmware. In this case, in the field 1j of the logical conditions of the format of the latest microinstructions of such microprograms, a zero code must be written. According to this code, the multiplexer 6 of logical conditions transmits an OT signal to its output as the value of the least significant bit of the address of the following microcommand.

If the signal is single (when the interrogation microprogram is executed), then addressing occurs to the return microcommand, to the interrupt microprogram. If the signal OZ is zero, i.e. if the interrupt firmware is not executed, then the next microcom of the current firmware is addressed.

In the field of the end of the command of the last microcommand unit is written. The conjunction of this QC signal with a single PB signal, formed by the first element 11, enables the operation of the comparison circuit g. If the priority code at the input A of the circuit 7 of the newly arrived at the input 19 of the operation code of the firmware device is greater than the priority code at the input B of the circuit 7 of the interrupted section

five

0

the firmware of the OT is not formed. In this case, the device works as in the implementation of an interrupt, i.e. A new firmware is being executed, the code of which is received at the input 19 of the device, and the previously lower-priority firmware that was interrupted earlier is waiting for its turn. The signals permitting the operation of the comparison circuit 8 and the return register 5 are not generated. With the start of the new firmware, the QC signal becomes zero and the first And 11 element blocks the operation of the comparison circuit 7,

If the priority code of the new operation is less than or equal to the priority code of the section where the previously executed firmware interrupted, comparison circuit 7 generates a signal OT. By this signal the address multiplexer A passes the address code from the second register output to the register 2 5 return. On the falling edge of the clock pulse 7 from the first output 14 of the generator 14, the return code to the interrupted firmware is entered into the register 2 addresses.

As soon as the first microcommand of the interrupted firmware appears at the outputs of block 1, the QC signal disappears (since the interruption does not occur in the last and last but one microprogram of microprograms) and, accordingly, the enabling signal at the control input of the comparison circuit 7.

On the falling edge of the OZ signal, the one-shot 15 is triggered and zeroes the return register 5. Next, the device works in the same way as the algorithm described.

In the format of the last microcommand, the last firmware, in addition to the unit in the 1j field at the end of the command, also records the unit in the highest bit category pol C address, which corresponds to the output 24 field 1j of the address,

The clock pulse of the second output 14.1 of the generator 14 clock pulses with its falling edge allows the code of the last micro-operation to be written to the register of 3 micro-operations. Conjunctions of the same impulse T, s

signal QC and a single signal from the output 24 of the field 1, j of the address of block 1, formed by the second element And 12, is a signal KP, This signal is fed to the R input of the trigger

five

0 5

0 5

0

five

Q

five

13 starts and puts it into zero state.

In this case, the operation of the clock pulse generator 14 is prohibited and the operation of the device is terminated.

Claims (1)

Invention Formula A microprogram control device containing a microprogram memory block, an address register, a micro-operation register, an address multiplexer, a return register, a logic conditions multiplexer, a first comparison circuit, a second comparison circuit, a trigger trigger, a clock generator, the And element, a second And element, and an input the device command code is connected to the first information input of the address multiplexer, the output cat (5 connected to the information input of the address register, the output of which is connected to the address input of the memory programs whose microoperations field output is connected to the microoperations register information input, the output of which is the device microoperations HOD15M, the output of the code field of the logic conditions of the firmware module of the microprograms is connected to the control input of the multiplexer logical conditions, the output of which and the output of the memory field of the memory block firmware are connected respectively to the second information input of the multiplexer, the address and the first information input of the return register, the first output of which is connected to the third one; address of the multiplexer address, the output of the modified address of the memory block of the firmware is connected to the first information input of the multiplexer logic conditions, the input logical conditions of the device are connected to the second information input of the multiplexer logical conditions, the start input of the device is connected to the installation input of 1 trigger start, the output of which is connected to the start input of the clock pulse generator, the first and second outputs of which are connected respectively to the synchronization inputs of the address registers and mi Operations, in order to expand the field of application of the device by ensuring that the device operates in the priority interrupt mode, it contains the first and second OR elements, the one-vibrator, the input priority code group of the device command input code being connected to the first information input groups of the first and the second comparison circuit, the first group of outputs of the return register is connected to the group of inputs of the first OR element, the output of which is connected to the first input of the first AND element, with a gate input to second comparison circuit and ten with the first input of the second element I, with the first input of the second element IL with the second input of the first element I, the output of which is connected to the S1DIM gate of the input of the first comparison circuit, the output of which is connected to the first control input of the multiplexer of the address and the start input of the single vibrator which is connected to the input The settings in the return register, the output of the second comparison circuit is connected to the enable input of the recording of the return register and the second input to the second the third information input of the multi 15 element OR, the output of which combines the logical conditions, the second group of outputs of the return register is connected to the second group of information inputs of the first comparison circuit, the outputs of the priority code field of the microprogram memory block 20 are connected to the second group of information inputs of the second comparison circuit and the second information input of the return register, the output of the sign of the end of the command 25 of the firmware memory block is connected with the second control input of the address multiplexer, the second output of the clock generator is connected to the synchronization input of the return register and the second input of the second element AND, the output of the higher bit of the address of the address of the memory module of the microprogram is connected to the third input of the second element AND whose output is connected to the installation input in the On start trigger. FIG. 2 with the first input of the second element AND, with the first input of the second element OR, with the second input of the first element AND, the output of which is connected to the strobe-U1DIM input of the first comparison circuit, the output of which is connected to the first control input of the multiplexer address and the start input of the one-vibrator, the output of which connected to the setup input in the O return register, the output of the second comparison circuit is connected to the enable input of the recording of the return register and the second input of the second it with the second control input of the address multiplexer, the second output of the clock generator is connected to the synchronization input of the return register and the second input of the second element, the output of the high bit of the address of the address field of the microprogram memory unit is connected to the third input of the second element, whose output is connected to the installation input in the On start trigger. pp WITH on V а / I о Arrival of oneflQtfuti to ffxoff fS i / CfnpoL cmffc Write ff register S SosSpama addresses following foofeu / iff fnefii / gnaw mp recording adrsmoeo but postutlvsheeo on SxodtA is an organizer & a pezucmp 2 offpeca The performance of the operation of interrupts & a and c isnomnynn using the amine no9npoijajaMM of the dry. operasgl the end J - records of 6pezucmp 2 address code from the reyler 5 ffffsffflama, 1LupanoA to the register 5 ozbraga 6 initial state Read mn / 73V 1 record i) LOL 2 addresses LZU1 moa addresses next mn in pftucmp 2 addresses -J