SU1711168A1 - Program run-time monitor - Google Patents

Abstract

The invention relates to computing and can be used to control the course of a program in multi-program computing systems with a dynamically changing priority of program execution. The aim of the invention is to expand the scope. The device contains a counter, a block of OR elements, a first, second and third block of AND elements, two registers, a clock generator, a delay element and K memory blocks, each of which contains a trigger, a second delay element, an OR element, a comparison circuit, a NOT element. , two registers, two elements I. The device provides memorization and restoration of the remaining execution time To interrupted programs. 2 Il.

Description

cl

WITH

The invention relates to computing and can be used in multiprogramming computer systems with dynamic priority of programs being executed.

The purpose of the invention is to expand the scope.

FIG. 1 shows a block diagram of the device; in fig. 2 is a block diagram of a memory block.

The device contains a counter 1, the overflow output of which is a device error output 2, and the counting input is connected to a 3 clock pulse generator, a block of elements OR 4, the first group of inputs of which is a group of inputs 5 that specify the maximum program execution time, register 6, group the inputs of which are a group of 7 inputs for setting the device program identifier, a delay element 8 whose input is an input 9 of the device interrupts, the second and first blocks of And 10 and 11 elements, the third block of And 12 elements, he first input of which is an input device 1.3 reduction interrupted program, a group of 14-114 K-K of blocks of memory, each

of which contains a trigger 15, the output of which is the output 16 of the memory block 16, the element OR 17, the first and second inputs of which are respectively the input 18 of the reading and the input 19 of the memory block reset, the element NOT 20, the delay 21, the first Element 22, the second input of which is the memory recording entry 23, comparison circuit 24, the second input of which is the first input 25 of the program identifier of the memory block, the second And 26, whose output is the output 27 of the memory, registers 28, 29,

about

00

the outputs of which are the outputs 30 and 31 of the memory block, and the information inputs are the information inputs 32, 33 of the memory block. Input 34 is a device reset input.

The device works as follows. At the beginning of the operation of the device, the reset signal is fed to the input 34, which is then transmitted to the inputs 19 of each of the blocks 14. The memory blocks 15 are reset to the free state. At the moment of launching each program, the additional code for its maximum execution time is written to counter 1, using input 5 and block 4, and the program identifier code is entered into register 6 through input 7. In the course of program execution, clock pulses from generator 3 are sent to the counting input of counter 1. If the execution time of the program exceeds the maximum allowed time, an overflow signal is generated at the corresponding output of counter 1, which through the output

2 devices enters the interrupt system. In multiprogramming mode, it is possible to interrupt this program to execute higher priority programs. In this case, naturally, it becomes necessary to save and restore the code of the remaining execution time of the interrupted programs.

The interrupt signals are fed to the input 9 of the device and then through the element 8 to the input 23 of the unit 14-1. In addition, the interrupt signals are sent to blocks 10 and 11 elements, and in this case, from the output of register 6 to the input 32 of memory block 14-1, a code identifying the program to be interrupted is fed, and from counter 1 to the input 33 of memory block 14-1 code of the remaining execution time of this program. Thus, when an interrupt signal is received, conditions are created for recording the identifier of the interrupted program in block 14-1. After this code is recorded in block 14-1, information from outputs 30 and 31 of block 14-1 is fed to inputs 32 and 33 of block 14-2. The signal from output 16 of block 14-1 is fed to input 23 of block 14-2 and initiates the overwriting of information from block 14-1 to block 14-2. After recording information about the interrupted program in block 14-2 at output 16 of this block, a signal is generated, which is transmitted to input 18 of block 14-1. Block 14-1 enters a free state. Similarly, the information about the interrupted program is copied from the i-ro memory block to i-1, provided that the i-1st memory block is in the free state.

The latest information about the first interrupted

the program is placed in the K-th memory block, the second interrupted program is placed in K + 1st, and so on. After recording the information about the interrupted program, the execution begins.

the program that caused the interrupt. At the same time, the additional code of the maximum permissible program execution time is again entered into the counter 1 via block 4, and through the information input 7 into the register 6

0, a code identifying the program itself is entered.

When returning to the processing of interrupted programs, a code identifying the recoverable

5, a program that is recorded in register 6. In addition, a recovery signal is sent from input 13, initiating the transmission of the code of the program being restored through block 12 to inputs 25 of each of blocks 14

0 memory. At the output 27 of that of the blocks 14, in which the obtained program identifier code coincides with the stored code, an additional code of the remaining execution time being generated is generated

5 programs. This code is transmitted through the block of elements OR 4 to the information input of the counter 1. If the additional code of the remaining time is read from the i-block of the memory block, the block 14-i of the memory goes into a free state. If the i-1 st memory block of group 14 is in a busy state, conditions are created for overwriting information from the i-1 th memory block to block 14-i. After rewriting the i-1st block of memory

5 enters the free state, and if the i-2 st memory block is in a busy state at that moment, the information from it is copied to the i-2 nd memory block, etc. Thus, the information stored in

0 blocks 14, always running as far as

it is possible, to the K-th block 14-K. In time

run the restored program

The device works in the usual way.

Memory unit 14 operates as follows.

5 way. At the time of launch, input 19 is given a signal that, having passed through the OR element 17, resets the trigger 15 to the zero state, which corresponds to the state of the free memory block, and allows writing information to the registers 28 and 29. Moreover, the register 28 records the code identifying the program, and in register 29 the additional code of the remaining execution time of the program. In5 formations located in registers 28, 29 can be read out respectively from outputs 30 and 31 of the memory block. The signal that permits recording through the element 22 and the delay element 21 is transmitted to the input of the trigger setup 15, which leads to switching

trigger in one state. The memory unit goes into a busy state.

To read information from memory block 14, the program code is read to input 25, which is transmitted to the second input of comparison circuit 24 and compared with the code stored in register 28. When the codes coincide, the signal from the comparator output goes to the second input of the And 26 element. The output of the register 29 to the output 27 of the memory unit is transmitted the additional code of the remaining execution time of the program, the information about which is stored in this memory unit. In addition, upon successful comparison, the signal from the output of the circuit 24 also enters through the OR element 17 to the reset input of the trigger 15, as a result of which this memory block goes into the free state.

Claims (1)

Invention Formula A device for monitoring program progress, containing a block of OR elements, a counter, a clock pulse generator, the first block of AND elements, and a group of inputs specifying the maximum execution time of a device program connected to the first group of inputs of an OR block whose output group is connected to a group of installation inputs the counter, the counting input of which is connected to the output of the clock generator, the information output and the overflow output of the counter are connected respectively to the information input of the first electric unit And error output device, characterized in that, in order to expand the scope of application due to the possibility of controlling the duration of programs that allow changing priorities of interrupted programs, the second and third blocks of And elements, delay element, register, group are entered into it from K-memory blocks. (K is the number of interrupted programs), the interrupt input of the device is connected to the building inputs of the first and second blocks of elements I and through the delay element “to the recording input of the first memory block of the group, the input of setting the identification code of the program of the device is connected to the information the register input and the information input of the third block of elements I, the gate input of which is connected to the input of the sign of the restoration of the program The output of the register is connected to the information input of the second block of elements I, the output of the third block of elements I is connected to the first information inputs of the memory blocks of the group, the input of the initial installation of the device is connected to the inputs of the initial installation of the memory blocks of the group, the outputs of the first and second memory blocks of the group connected, respectively, to the first and second information inputs of the first memory block of the group, the occupancy output of each memory block of the group, except the last one, is connected to the recording input of the subsequent memory block, The second and third information outputs of the i-ro group memory block (1-in) are connected to the corresponding information inputs of the i + 1 group memory block, the third information output of the i-ro group memory block is connected to the corresponding input of the second group of block inputs the OR elements, the output of the i-ro memory block of the group, except the first, is connected to the read input of the i-1 group memory block, each group memory block contains the OR element, a trigger, two registers, a comparison circuit, two elements And, the element is NOT and the element of delay, with the first and second inputs the OR element is the read input and the input of the initial installation of the memory block, the output of the OR element is connected to the zero input of the trigger, the output of which is the occupancy output of the memory block and through the element is NOT connected to the first input of the first AND element, the second input of which is connected with the memory block write input, the output of the first element I is connected to the record inputs of the first and second registers, and through the delay element to the single trigger input, the information inputs of the registers are the second and third instants, respectively the formation inputs of the memory block, the outputs of the registers are connected respectively to the first input of the comparison circuit and the first input of the second element AND are the first and second information outputs of the memory block, the output of the comparison circuit is connected to the second input of the second AND element and the third input of the OR element, the second the input of the comparison circuit and the output of the second element And are respectively the first information input and the third information output of the memory block. FIG. I