SU1596333A1 - Device for detecting errors in data transfer - Google Patents

Abstract

The invention relates to digital computing and can be used in control devices for transmitting digital information. The purpose of the invention is to increase the diagnostic capabilities of the device due to the constant monitoring of the transmitted information. The device contains a memory block 1, a synchronization block 2, an address register 3, a data register 4, a base register 5, a decoder 6, a comparison block 7, a HE element 8, an AND 9 element, two buffer memory elements 10.11, a gate input 12 , synchronization input 13, error output 14, two groups of 15.16 information inputs - outputs, a group of 17 address inputs, an input 18 of the record, an input 19 of the reading, a group of 20 monitored inputs of the data address, an input-output 21 of the request-confirmation. The device performs a bit-wise comparison of the information outputted to the output device with the reference information stored in the memory unit and forms a copy of the output information for analysis by external computing means. A positive effect is achieved by introducing into the device a synchronization unit, a memory unit, a decoder and buffer elements. 2 hp ff, 3 ill.

Description

The invention relates to digital computing and can be used in control devices for transmitting digital information.

The purpose of the invention is to increase the diagnostic capabilities of the device due to the constant monitoring of the transmitted information.

FIG. 1 shows a functional diagram of a device for detecting errors in the transmission of information; in fig. 2 - functional block diagram; in fig. 3 - a functional block diagram of the memory.

The device (Fig. 1) contains a memory block 1, a sync flare 2, an address register 3, a data register 4, a base register 5, a decoder b, a comparison block 7, a HE element 8, an AND 9 element, two buffer elements 10 and 11 ti strobe device input 12, device sync input 13, device error output 14, two groups 15 and 16 information input-output devices, device address group 17, device write input 18, device read input 19, group 20 monitored inputs of device address data and the input-output 21 of the request-confirmation device va.

The synchronization unit (Fig. 2) consists of three triggers 22-24, three counters 25-27, three elements NOT 28-30, two elements AND 31 and 32, a decoder 33, and element OR 34.

The memory block (Fig. 3) includes two accumulators 35 and 36, a decoder 37, two elements OR 38 and 39, an AND-NOT element 40, an AND 41 element and two elements NO 42 and 43.

A device for detecting errors in the transmission of information outputted to output devices is intended to work within the computational units of a multiprocessor system having systemic address and data backbones, and operates in conjunction with a computational unit, controlling information transmitted over the system backbone of data to output devices.

The device works as follows.

Before the device starts to control the group of 20 inputs of the address-data, through which information is transmitted to the output device, the external device (for example, the computing unit) forms the address through the group 17 of the address inputs and the groups 15 and 16 of the information inputs in the memory block 1 the sector, and in the lower memory bank (accumulator 36) the reference information is formed in the forward code, and in the older bank (accumulator 35) the information in the inverse code is formed. In addition, the external computing unit writes in the base 5 register the base address of the exchange sector. Record in the register 5 bases

carried out from a group of 16 information inputs provided that the address of the register 5 is decoded by the decoder 6 and the recording signal is generated.

The information entering the device through the monitored inputs of the data address of group 20 is accompanied by a strobe signal from input 12. The positive edge of this pulse is information from the monitored inputs

5 is recorded in the address register 3 and the data register 4. In addition, a synchronization unit 2 is triggered by a gating pulse, which, at the input-output 21, generates a request for a revision request to the memory unit 1. By

When the confirmation is received, the synchronization unit generates a signal at its second output, and the information from the registers 3-5 and control signals from the outputs of the elements 10 and 11 is allowed.

5 The information from the output of the register 4 is recorded in the accumulator 35 and compared with the reference information supplied from the accumulator 36. The comparison is made at the comparison unit 7, the result of the comparison

0 is gated from the first output of the synchronization unit 1 and is output at error output 14. Next, the synchronization unit generates at input-output 21 a signal indicating the end of the cycle of accessing the unit 1 block.

The error signal can be input to an external computing unit interrupt, which, after shutting down the device, can analyze the results of monitoring by reading information from memory block 1.

The synchronization unit operates as follows. The signal from input 12 to trigger 22 is recorded O, and a single signal

5 from its inverse output, it unlocks the element And 31. At the counting input of the counter 26, pulses are received from the synchronization input 13,. As a result, an inverted pulse is generated at the input-output 21

0 low level, having a duration equal to the period of the synchronization frequency. This pulse is a request for a memory access request. The same impulse, inverted by the element NOT

5, 30 is fed to the counting input of the counter 27. The potential of a logical unit is established at the negative front of this pulse at the output of the counter 17.

Element 32 is unlocked by this potential, and trigger 22 is set to

single state. With a low signal from its output, trigger 22 blocks further sync pulses from sync input 13 to ratter 26. In this idle state, the block remains until a low even response pulse arrives at input / output 21. This impulse signals unit 2 about the possibility of accessing block 1. A pulse that is inverted by the NOT 30 element enters the counting input 27, and 27 through element 32 to the C input of the trigger 23. Positively, by the front of this pulse, the trigger 23 is set to the zero state. The negative front of the same pulse at the output of counter 27 establishes a zero potential that blocks element 32. A high level signal from its inverse output triggers 23 unlocks trigger 24, and low signals from the direct output of trigger 23 allows the counter 25 and decoder 33 to work. The counter 25 and the decoder 33 perform the function of a pulse distributor. The low level pulse from the first output of the decoder enters the R input of trigger 24 and sets it to the zero state. A low level signal appears at the output of trigger 24.

With this signal, the address register 3 is connected to block 1, the data register 4, base register 5, active signals of low level are output from the outputs of elements 10 and 11 on the write and read lines. The contents of register 3 of the address form the lower part of the address, and the contents of register 5 of the base form the upper part of the address of the exchange sector in memory block 1. The information recorded in data register 4 is fed to a comparison unit 7 and to a memory accumulator 35, in which it is recorded by a recording signal. At the same time, the reference information is read out from the memory accumulator 36 and is fed to the second inputs of the comparison unit 7.

After the end of the transients, the decoder 33 from the second output emits a low-level pulse, which unlocks the element 9, and the signal from the output of the comparison block 7 arrives at the output 14 of error. The same impulse arriving at the input 6 of the trigger 24, sets the trigger 24 to the one state by a positive front. The trigger 24 by the high level signal at its output disables the 3 address register, the 4 data register and the 5 base register from memory block 1. After that, the third output of the decoder 33 produces a low-level pulse, which through the OR 34 element enters output-output 21 and signals the end of the cycle of accessing memory block 1, followed by im- - ;. pulse on the fourth output of the decoder 33 sets to its initial state the counter 27, the counter 26 and the trigger 23. The trigger

23, in turn, with a signal from its direct output, sets the counter 25 to the initial state and blocks the decoder 33.

If the compared information matches, the inverse information in the storage

The exchange sector is replaced with the monitored information in the forward code. Match the contents of drives 35 and

36 of the exchange sector indicates reliable transmissions. Presence of inverse

a byte of information in the exchange sector accumulator 35 is a sign that this byte of information was not induced. In all other cases, the discrepancy between the contents of the accumulators 35 and 36 of the exchange sector indicates an error when transmitting data to the output device.

Memory unit 1 operates as follows. When an external computing unit performs a write operation in block 1, a low LEVEL signal is present at input 18 of the recording; and at output 19 of reading, a high level signal. Thus, the low level signal from the input 18 of the recording comes

to the control input of the first accumulator 35, and from the output of the element IS-NOT 40 - to the control input of the second accumulator 36. At the outputs of the elements OR 39 and AND 41, there are high-level signals, i.e.

the drive outputs are in the off state.

During a read operation, a high level signal is present at write input 18, as well. at the inlet of 19 readings - low. Thus, at the control inputs of the drives connected one to the input 18 of the record, the other to the output of the element IS-NOT 40. there are high level signals. At the outputs of the elements OR 38 and AND 41 there appear signals of a low level, with which the outputs of both of these drives are connected to the inputs-outputs of the block.

When accessing the memory block 1 from the side of the functional units of the device for detecting errors in transmitting information, low-level signals appear at the inputs 18 and 19 of the write and read, resulting in a high-level signal at the output of the IE 40 element OR at the output of the element OR 39 - signal -, high level, at the output of the element; / And 11 - low level signal, and the information is recorded in the first accumulator 35 and read from the second accumulator 36.

Claims (3)

1. Device for detecting information transmission errors, containing an address register, a data register, a base register, a comparison block and an AND element, where the information inputs of the address and data registers form groups of monitored device information inputs, the group of address register outputs are connected to a group of device address inputs , the group of outputs of the data register is connected to the first group of information inputs-outputs of the device and to the first group of inputs of the comparison unit, characterized in that, in order to increase the diagnostic capabilities of the device due to bit-wise control of the transmitted information, a descrambler, a NOT element, the first and second elements of the buffer memory, a synchronization block and a memory block are entered in it, where the inputs of the register of address and data registers and the trigger input of the synchronization block are combined and connected to the gating input the device, the clock input of the synchronization unit is the INPUT of device synchronization, the first output of the synchronization unit is connected to the input of the element NOT, the output of which is connected to the first input of the element AND, the second input of the cat The first is connected to the output of the comparison block, the output of the AND element is the output of the device error, the second output of the synchronization block is connected to the read input of the data registers, the address, the base and the inputs of the first and second buffer elements, the output of the first buffer element is connected to the read input of the memory block and is connected to the input of the reader, the output of the second buffer element is connected to the gate input of the decoder, with the write input of the memory unit and connected to the input of the write device, the output of the decoder is connected to the input of base register records, the base register group of the base register is connected to the information group of the decoder inputs, to the group of address inputs of the memory unit and connected to the group of device address inputs, the first group of information inputs / outputs of the memory unit is connected to the first group of information inputs and outputs of the device, group the information inputs of the base register are combined with the second group of inputs of the comparison unit, with the second group of information inputs-outputs of the memory unit and is the second group of information inputs-outputs of the device oystva, input-output synchronization unit is input-output request-acknowledgment device. 2, The device according to p. 1, characterized in that the synchronization unit comprises first, second and third counters, a decoder, first, second and third triggers, first, second and third elements NOT, element OR, first, second elements AND, the synchronization input of the first trigger being input start the unit, the installation input in G and the inverse output of the first trigger are connected respectively to the output and to the first input of the first element I, the second input of which is combined with the counting input of the first counter and is the clock input of the block, the output of the first element I connected with the counting input of the second counter, the zero input of which is combined with the installation input 1 of the second trigger, the zero input of the third counter and connected to the first output of the decoder, the output of the second counter connected to the input of the second element NOT whose output is combined with the output of the OR element, with the input of the third the element is NOT and is the input-output of the request-confirmation block, the output of the third element is NOT connected to the first input of the second element AND and to the counting input of the third counter, the output of which is connected to the input of the first element This is NOT with the second input of the second element AND, whose output connected to the synchronization input of the second trigger, the inverse output of which is connected to the installation input 1 of the third trigger; the direct output of the second trigger is connected to the enable input of the decoder and to the zero input of the first counter, the output group of which is connected to the group of inputs of the decoder, the second output of which is connected to the installation input into the third trigger, the synchronization input of which is connected to the third output of the decoder and is the first output of the block, the fourth output of the decoder connection the first input of the element And And, the second input of which is connected to the output MSB first counter, the output of the third flip-flop is a second block output. information inputs of the first and second triggers are connected to the logic potential of the zero block of the block, information the input of the third trigger is connected to the potential bus of the logical unit of the block. 3. The device according to claim 1, wherein the memory unit contains the first and the second drive, the decoder, the first and second elements are NOT, two elements OR, element NAND, element AND, the first inputs of the OR elements are combined and are the input of the block, the second input of the first element OR is combined with the input the first element is NOT, with the write-read input of the first accumulator and is the block write input, the output of the first OR element is connected to the first inputs of the IED elements. And with the input of the second element is NOT. the output of which is connected to the second input of the second OR element, the third input of which is connected to the output of the decoder, to the enable inputs of the first and second drives, the output of the second OR input is connected to the read input of the first storage device and to the second input of the AND element whose output is connected to the input permitting the reading of the second accumulator, the write-read-entry of which is connected to the output of the NAND element. the second input of which is connected to the output of the first element NOT, the group of address inputs of the accumulators are combined with the group of inputs of the decoder and are a group of address inputs of the block, the input-output groups of the first accumulator is the first information group of inputs-outputs of the block It is the second information group of block I / O.