SU1483453A1 - Request source address generator - Google Patents

Abstract

The invention relates to computing and can be used in conjunction with a microcomputer peripheral devices. The goal is to expand the scope by eliminating the requirements for synchronizing the request signals. The device contains the register 1, the element AND 2, the counter 3, the decoder 4, the multiplexer 5, the comparison circuit 6, the element AND-NOT 7 and the group of elements AND 8. The device eliminates the need to re-serve the same request regardless of its duration and does not impose any requirements for the formation of the request signal by the peripheral device. 1 il.

Description

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The invention relates to computing and can be used to interface microcomputers with peripheral devices.

The purpose of the invention is to expand the field of application of the device by eliminating the requirements for the synchronization of request signals.

The drawing shows the functional diagram of the device.

The device contains a register 1, an element AND 2, a counter 3, a decoder 4 multiplexer 5, a comparison circuit 6, an element NE-7, a group of elements AND 8, an output 9 of the combined device request, a clock input 10 of the device, inputs 11 of the device requests, outputs 12 device data, device address inputs 13, device write input 14, device 15, 16 O inputs.

The device works as follows.

In the initial state, the service requests are not received and on the inputs 11 are signals O, which provide a value O at the output of multiplexer 5, which corresponds to the absence of a signal at output 9 and ensures the passage of clock pulses from the clock input 10 through element 2 to the input of counter 3 At address inputs 13, signals with levels O which are written to register 1 by a signal at input 14 are written to register 1. O, acting on the last output of decoder 4, prohibits, through elements 8, from reading data from outputs 12 of the device. The signals O from the outputs of register 1 are fed to the inputs of the comparison circuit 6 and ensure the presence of 1 hectare of the output of the comparison circuit 6.

At the output of counter 3, code combinations are formed, which, arriving at the control inputs of multiplexer 5, connect the output of multiplexer 5 to its information inputs

When a request signal occurs at one of the inputs 11 and the code combination at the output of the counter 3 coincides with the address of the requester initiator at the output of multiplexer 5, Wits 1, the closing element IS-NOT 7, which will prohibit further receipt of clock pulses through the And 2 element at the input counter 3, the output of the counter will be fixed

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the address of the requestor, and the output of the 9 signal is formed combined request.

From the external control unit, the input of register 1, via address inputs 13, receives a command to read the address of the initiator, which, according to the signal at input 14 of the record, writes c to register 1 and is fed to the input of the decoder 4. With this command, a signal 1 appears at the first output of the decoder 4, allowing the issuance of the address of the initiator of the request to the outputs of 12 data.

As soon as the external control device takes over the incoming request, the address of the request initiator is sent to the inputs of register 1, which is written to register 1 by a signal at record input 14. As a result, the address of the request initiator is sent to the second inputs of the comparison circuit 6, which is compared with the code combination that exists at the outputs of counter 3 and is also the address of the requester.

Thus, at the output of the comparison circuit 6, the VIT signal O, the opening element NAND 7, which through the AND 2 element permits the passage of clock pulses to the input of the counter 3, and the device continues to search for the next request. Subsequent requests serve in the same way.

O are fed to inputs 15 and 16 of multiplexer 5, since the zero and one states of counter 3 and register 1 are used to set the device to its initial state and to read the address of the requestor from the group of elements And 8, respectively.

At the end of the polling cycle, a transfer signal appears at the output of counter 3, which is fed to the reset input of register 1 in the initial zero state.

Claims (1)

Invention Formula A device for generating the source address of the request containing a register, a decoder, a multiplexer, groups of elements nd, a counter, an element AND, the counter input of the counter is connected to the output of an element AND whose first input is connected to the clock input of the device, the outputs of elements AND of the group are address outputs the initiator of the device request; the first inputs of the elements AND of the group are connected to the corresponding outputs of the counter and to the corresponding control inputs of the multiplexer, the output of which is connected to the output of the combined request Triplets, second inputs of elements AND groups are connected to the last output of the decoder, characterized in that, in order to expand the scope of application by eliminating the requirements for synchronization of request signals, a comparison circuit and an IS-NOT element are introduced, and the information inputs of the register are the addresses of the device requester initiator, the register outputs are connected to the decoder inputs and the first group of inputs of the comparison circuit, the second group of inputs of the comparison circuit is connected to the counter outputs, the output of the comparison circuit is connected to the first input of the AND-NOT element whose output is connected to the second input of the AND element, the transfer output of the counter is connected to the input reset a register whose clock input is a device record input, device request inputs are connected to the multiplexer information inputs except the first and last, and the first and last multiplexer inputs connected to the input of the logical zero of the device, the output of the multiplexer is connected to the second input of the element NAND "