SU1545225A1 - Device for interfacing two trunks - Google Patents

Abstract

The invention relates to computing and can be used in multichannel (multiprocessor) systems for providing access to a shared resource. The aim of the invention is to increase the speed of its operation by reducing the waiting time for providing a resource when requesting only one of the highways. A device containing two trunk switches, two address registers, a memory block, six AND elements, two triggers, two zone decoders, two groups of AND elements, a pulse generator and a NOT element, two triggers are entered, three AND elements and two OR elements . At the same time, the corresponding additional trigger captures the request from this highway in the half-cycle of the clock frequency following which the main trigger of this highway did not respond. When a request is fixed from a given highway, the second highway is blocked, and when requests are made at the same time, the priority of the routes is random. 2 Il.

Description

The invention relates to computing and can be used in multi-channel computing (multiprocessor) systems for providing access to a shared resource.

The aim of the invention is to increase the speed of operation of the device when the combined trunk is provided upon request in this half-period of the following clock pulses from only one of the highways.

Figure 1 shows the functional diagram of the device; figure 2 - timing charts of his work.

The device contains block 1 of memory, switches 2 and 3 lines, registers 4 and 5 addresses, bus 6 information lines of the device, decoders 7 and 8 zones, 9 pulse generator, first JO and second 11 triggers, groups of elements 12 and 13, first , th, third, fifth, second, fourth and sixth elements AND J4-J9, element NOT 20, inputs 21 and 22 of reading, levels of 23 and 24 recording inputs, highway 25 and 26 of information inputs - outputs, buses 27 and 28 of inputs address synchronization, bus 29 and 30 outputs of the device response synchronization, the third 31 and fourth 32 triggers, the seventh - ninth element Options and 33-35, or 36 elements and 37.

The device works as follows.

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Registers 4 and 5, along the Fronts of the pulses on Tines 27 and 28, add address codes from highways 25 and 26. When an address coincides with the address area of memory block 1, decoders 7 and 8 of the zone output signals that are held at the information inputs triggers 10, 11, 32, and 33, until the contents of registers 4 and 5 change.

If one request arrives, then And 33 output has a resolving potential, and therefore And 34 and 35 are open. The positive front of the first half-wave of clock pulses from the generator 9 enters the sync trigger of trigger 10, from the element NOT 20 through the element AND 34 to the synchronous input of the trigger 11 from the element HE 20 to the synchronous input of the trigger 11, ac output of the generator 9 through the element 35 on the synchronous input of the trigger 32.

Depending on which request period arrives at, the corresponding trigger 10 (P) or 31 (32) will be installed first and, through the OR 36 (37) element, will transmit a signal that the 32 (31) and H (10) triggers are disabled. request on the second channel (trunk) before the unified trunk is released.

In the subsequent half-period, after one of the triggers 10 (11) or 3 (32) fires, the other one will trigger. When the element OR 36 (37) is triggered, the corresponding switches 2 (3) are opened. In this case, the direction of their transfer is determined by the presence of one of the external signals, Read or Write.

These external signals also control the operation mode of unit 1 via AND elements 14 (17) or 15 (18).

The address in block 1 comes through the elements And 12 (13) from registers 4 (5). Elements 16 and 16 control the arrival on the corresponding buses 29 (30) of the response synchronization signal from the memory, which carries information about the end of memory access.

If during any half-cycle of the clock signal from the generator 9, requests from both highways are received, then the output potential of the AND 33 element causes a forbidding potential that closes the AND 34 and 35 elements. In the next half-cycle of clock pulses, only one can operate according to a random law of triggers 10 or 11, giving access to the appropriate trunk. Further, the operation of the device is carried out similarly. At the moment of release of the combined highway, at the output of the element And 33 the resolving potential again appears, since there is a request of only one of the lines.

In this case, from the output of one of the elements 34 and 35, at this moment, a sync signal appears at the input of the flip-flops 31 or 32. And if it was a flip-flop cocked when accessing the combined highway, then it will return to its original state , otherwise, by the front front (of the next half period) clock pulse.

At the same time, the signal from the output of the OR 36 (37) elements is removed, and therefore, the Reset signal from the corresponding inputs of the trigger 11 (10) and 32 (31) is removed, which allows the latter to go into the on state and capture the combined mainstream.

Further, the provision of the trunk and operation of the device is carried out similarly to the described above.

However, taking into account that the set trigger when requesting from the first line can be reset at the moment of removing the request itself, i.e. without waiting for the clock pulse to come, the likelihood of providing a combined highway for working with the second highway in the next half period of clock pulses or after one half period increases.

The diagrams (Fig. 2) illustrate various variants of the device operation under various initial conditions of its operation by the moment of providing (releasing) the highway.

Claims (1)

Invention Formula A device dp interface of two trunks, containing six elements AND, a memory block, a group of information inputs-outputs of which are connected to the first groups of information inputs-outputs of the first and second commutators of the lines, the second groups of information inputs-outputs of which are corresponding groups of input-output devices for connecting to the information pins of the first and second highways and connected to groups of information inputs of the first and second address registers, groups of outputs of which are connected respectively to the first inputs of elements of the first and second groups and groups of inputs of the first and second zone decoders, generator pulses, the output of which is connected to the synchronous input of the first trigger and through the element NOT to the synchronous input of the second trigger, and the information inputs of the first and second triggers are connected to respectively, with the outputs of the first and second zones of the zone, the reading input of the memory unit is connected to the combined mounting OR outputs of the first and second elementons I. The first inputs of which are the corresponding inputs of the device for connection to the reading buses of the first and second highways and connected to the first control the inputs of the first r of the second commutator of the highway, the second control inputs of which are connected respectively to the first inputs of the third and fourth elements of the AND, and are the inputs of the device for connection to the bus records of the first and second highways, outputs of the third and fourth elements And are combined by assembly 1 Jui and connected to the write input of the memory unit, the group of address inputs of which are connected to the outputs of elements And of the first and second groups, and the output of the response sign - respectively to the first inputs of the fifth and the sixth And elements, the outputs of which are the corresponding outputs of the device for connecting five 0 five 0 five 0 The first and second address register sync buses are the corresponding device inputs for connecting the first and second line address synchronization chips, characterized in that, in order to improve the speed of the device, three elements are inserted into it. And, two elements OR and two triggers, with the information inputs of the third and fourth triggers connected respectively to the outputs of the first and second zone decoders and the first and second inputs of the seventh element Inverse output connected to the first inputs of the eighth and ninth elements And, the second inputs of which are connected respectively to the outputs of the element NOT, and the pulse generator, and the outputs - respectively with the synchronous inputs of the third and fourth triggers, outputs connected respectively to the first inputs of the first and second elements OR , the second inputs of which are connected respectively to the outputs of the first and second triggers, the reset inputs of the first and third triggers are connected to the output of the second element OR, the second inputs of the second, quarter The second and sixth elements of the AND, the synchronous input of the second commutator and the second inputs of the AND elements of the second group, the reset inputs of the second and fourth triggers are connected to the output of the first OR element, the second inputs of the first, third and fifth elements of the synchronous input of the first commutator of the trunk and the second inputs of the elements And the first group.