SU1539788A2 - Device for interfacing two buses - Google Patents

Abstract

The invention relates to computing, can be used in multichannel (multiprocessor) systems to gain access to a common shared resource, and is an improvement on the known device according to the author N1283781. The aim of the invention is to increase the reliability of the device. The goal is achieved by inserting the element OR, the third trigger and the AND-OR element into the device according to auth. N1283781, which form the permission signals to provide access to the shared resource and provide the "Record" and "Read" control signals from the selected lines to the input of the memory block only after setting the correct values of the address and data. 2 Il.

Description

 The invention relates to computing and can be used in multichannel (multiprocessor) computing systems in forming timing diagrams of switching and controlling devices in channels.

The aim of the invention is to increase the reliability of the device.

FIG. 1 shows the block diagram of the proposed facility; in fig. 2 - time diagrams of his work.

The device contains (Fig. 1) block 1 of memory, switches 2 and 3 of the trunks, registers 4 and 5 addresses, block 6 of switches consisting of zone decoders 7 and 8, generator 9 of pulses, triggers 10 and 11, elements 12 and 13 of the first and second groups, the first 14, third 15, p 16, second 17, fourth 18 and sixth 19 And elements and NOT 20 element, tires 21, 22 and 23, 24 reading and writing the first and second highways, information and address tires 25 and 26, buses 27 and 28 of exchange control, and buses 29 and 30 of the response of the first and second highways, element OR 31, element AND-OR 32, and trig ger 33.

The device works as follows.

In registers 4 and 5, the pulse fronts on buses 27 and 28 are entered by address codes from buses 25 and 26. When an address coincides with the address area of memory block 1 appears, the decoders 7 and 8 zones emit signals that are held for information inputs of triggers 10 and II until the contents of registers 4 and 5 change. Only one of triggers 10 and AND always works, because the signals of generator 9 are inverted to their sync inputs, for example, when trigger

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10 to the reset input of the trigger 11, a blocking reset signal is received, prohibiting triggering of the trigger 11 until the trigger 10 is reset, i.e. while the signal from the decoder is present 7. After the removal of this signal, the trigger 10 by the next control edge of the pulse from the generator 9 is reset, and the lock of the trigger I is released.

At the moment when one of the triggers 10 and 11 is triggered, the corresponding switches 2 or 3 open. In this case, the direction of their transfer is determined by the presence of one of the external signals Read or Write. These external pulses control the operation mode of unit 1, i.e. in a bidirectional trunk, either the word appears for writing in block 1, or the word is read from block 1 and enters the trunk.

The address in block 1 enters through AND 12 or 13 from register 4 or 5, depending on whether trigger 11 is turned on.

The control signals that determine the operation mode of block 1 (Read or Write) are received through the element 14 or 15, 17 or 18. The element 16 or 19 controls the receipt of the response synchronization signal from the memory 29 or 30 on the corresponding bus 29 or 30 which carries information about the end of access to the memory.

When accessing memory block 1, signals from the outputs of the trigger 10 and 11 are fed to the inputs of the element OR 31, the output of which is connected to the synchronous input of the trigger 33. At the same time, the information input of the trigger 33 is supplied with a potential corresponding to 1. The trigger 33 is set on the leading edge Signals on its sync input from one of the triggers 10 and 11. At the same time, they cannot work.

When the trigger 33 is set, a signal appears on its inverse output, which prohibits the operation of the elements 14, 15, 17 and 18.

At the same time, the respective switches are connected to the combined trunk, from the register 4 or 5 of the address, through the element 12 or 13, the address is supplied to the block 1 of the memory. Suppose that trigger trigger 10 is set. However, although at the first input of the first element and the AND-OR 32 element there is an enable potential, the trigger 33 is not reset until the enabling sync signal at the second input of this element I. Therefore, the Read or Write signal from the AND 14 or 15 element is not received in memory block 1, which allows the correct signals to be set at the information inputs of memory block 1.

When a signal appears on the second tail of the first element I of element 32, the trigger 33 is reset and the signal Read or Write is fed to the input of memory block 1. In this case, the required exchange cycle with the memory is performed.

The device works in a similar way when simultaneously requesting a combined trunk from two temporary devices (highways), since at first only one of the highways gets access.

F-mule invention

A device for connecting two highways by bus No. 1283781, that is, in order to increase the reliability of the device, a third trigger, an OR element and an AND-OR element are introduced into it, the first and second inputs of the OR element are connected respectively to the outputs of the first and second triggers, and the output - to the synchronous input of the third trigger, the reset input of the AND-OR element connected to the output, the first, second, third and fourth inputs of which are connected respectively to the output of the first trigger, the output of the HE element, the output of the pulse generator and the output of the second trigger, the third trigger output Hera is connected to the third inputs of the first, second, third and fourth elements I.

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Claims (1)

Claim Device for pairing two highways No. 1283781, characterized in that, in order to increase the reliability of the device, a third trigger, an OR element, and an AND-OR element are inserted into it, the first and second inputs of the OR element being connected respectively to the outputs of the first and second triggers, and the output to the sync input the third trigger, the reset input connected to the output of the I-IPI element, the first, second, third and fourth inputs of which are connected respectively to the output of the first trigger, the output of the element NOT, the output of the pulse generator and the output of the second trigger, the output of the third trigger connected to the third inputs of the first, second, third and fourth elements I. hi a st VV I 2212 LI