RU1784986C - Device for two processors addressing to common memory block - Google Patents

Abstract

The invention relates to the field of computer engineering and can be used in the construction of multiprocessor systems with asynchronous access of several processors to a common memory. The aim of the invention is to expand the scope of use. The device contains the first to tenth triggers, from the first to the sixth AND-NOT elements, a two-phase pulse generator, the first and second AND elements, the first and second address decoders. 2 ill.

Description

The invention relates to the field of computer engineering and can be used in the construction of multiprocessor systems with asynchronous access of several processors to a common memory.

Known devices for interfacing processors with a common memory block, containing four triggers, a pulse generator, and elements I. These devices provide asynchronously received requests from the first and second processors to access the shared memory block in order of receipt without prioritizing one of the processors . When the requests from two processors coincide in time, the devices provide their sequential access to the shared memory for the duration of one write or read cycle.

The closest to the invention in technical essence and the achieved result is a device for interfacing two processors with a common memory, which contains two address decoders.

two segment decoders, two array igomer registers, two switches, four transceivers, an encoder, a multiplexer, a pulse generator, eight triggers, six elements l. element AND NOT, five elements NOT ,, element OR. If the requests from two processors coincide in time, the device provides their sequential access to the common multi-block memory, i.e. Allows expanding the memory address space of each processor.

The disadvantage of this device is that it does not provide synchronization of access of processors to the shared memory during the exchange of information arrays. The purpose of such synchronization is to prevent one of the processors from reading the array from the shared memory at the same time that the other processor is updating information in the given array. The absence of this synchronization leads to the processor reading the array in which part of the information is old and some of the information is already

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updated. For a number of control systems operating in real time, this is not acceptable.

A known method for communicating processors through a common memory organized by the principle of a mailbox partially solves this problem. Fixed areas are allocated in the shared memory: the status mailbox and the message mailbox. One processor forms an array of information and an accompanying receipt, place them respectively in the mailbox of messages and status mailbox. The other processor, as soon as it is ready, accesses the mailbox of messages and, upon detection of a receipt about the availability of data in the corresponding mailbox of messages, sets up a receipt and reads an array of information.

In this case, for the prototype device, there may be cases where, for example, the first processor, before reading the array, executes the receipt analysis command, which at the given time indicates access permission. The second processor, before updating the information in the array, will also establish a request to analyze the receipt status for the given array. Since the shared memory is currently occupied by the first processor, a request to access the second processor to the shared memory will be delayed while the receipt of the receipt by the first processor. After the analysis of the receipt by the first processor is completed, his next command, by which he must change the state of the receipt to block the access of the second processor to the array, will be delayed due to the shared memory being used by the second processor. At the end of the analysis of the receipt by the second processor, its next command containing the entry in the receipt of the lock code for the first processor will be delayed, because the first processor is currently accessing the shared memory to change the receipt code. Thus, there is a non-zero probability that both processors, having analyzed the receipt, will simultaneously access the same array.

The purpose of the invention is to remedy this drawback, i.e. expanding the area of use by ensuring synchronization of access of processors to a common memory unit during the exchange of information arrays.

This goal is achieved in that in a device for accessing two processors to a common memory unit, containing

eight triggers, two AND-NOT elements, two address decoders, two AND elements, a pulse generator, and the inputs of the first and second address decoders are connected

5 to the first and second bus address of the device, respectively, and the outputs of the first and second address decoders are connected respectively to the data inputs of the first and second triggers, the outputs of which are connected

0, respectively, with the first inputs of the first and second AND elements, the second inputs of which are connected respectively to the first and second bus lines of the device, inverse outputs of the third and fourth triggers

5 are connected respectively to the first and second bus enable buses of the device, the clock inputs of the first and second triggers are connected respectively to the first and second bus synchronization exchange

0 devices, the outputs of the first and second elements AND are NOT connected respectively to the installation inputs of the fifth and sixth triggers, the ninth and tenth triggers are introduced, the third to sixth elements

5 AND NOT, with the direct outputs of the fifth and sixth triggers connected respectively to the data inputs of the third and fourth triggers and to the first inputs of the third and fourth elements AND NOT, the second inputs

0 of which are connected respectively to the first and second bus request device and the first inputs of the first, second and pth, sixth AND elements NOT, the second inputs of which are connected respectively with the first

5 and the second outputs of the pulse generator and the direct outputs of the seventh and eighth triggers, the installation inputs of which are connected respectively to the first and second buses of the installation of the initial state of the device, and the inverse outputs of which are connected respectively to the third inputs of the second and first elements NAND, fourth the inputs of which are connected respectively with the inverse outputs of the fifth and

5 of the sixth flip-flops and with the first and second bus barriers to access the device, the synchro inputs of the first and sixth flip-flops combined with the reset inputs of the third and fourth flip-flops respectively are connected to the first and second sync buses of the device’s exchange, respectively, the sync inputs of the third and fourth flip-flops are connected i respectively with the first and second clock buses of the device, the data inputs of the fifth and sixth triggers are connected to the bus of the zero potential of the device, the outputs of the third and fourth elements are NOT connected Nena respectively with said seventh and eighth clock terminal of flip-flops, the data inputs of which

respectively connected to the direct outputs of the ninth and tenth flip-flops, the data inputs, clock inputs and reset inputs of which are connected respectively to the bit of the first and second bus address of the device, the outputs of the first and second AND elements, the outputs of the fifth and sixth AND elements.

The combination of known elements in the device with newly introduced two triggers, four NAND elements with the indicated connections when organizing the operation of two processors on a common memory block with a standard combined address / data trunk (like MPI) allows each processor to capture a common block memory not one, but two consecutive accesses, which ensures reliable operation when exchanging arrays of information with asynchronous receipt of requests for accessing the memory from both processors, i.e. expand the scope of use of the device.

In FIG. 1 shows a diagram of a device; in FIG. 2 is a diagram of using the device in conjunction with two processors.

A device for accessing two processors to a common memory unit (Fig. 1) contains triggers 1, 2, NAND elements 3, 4, a pulse generator 5, triggers 6-9, NAND elements 10,11, triggers 12, TK , elements AND 14, 15, triggers 16, 17, decoders 18, 19, elements AND-NOT 20, 21.

In FIG. 2 shows a device 22 for accessing two processors 23 and 24 to a common memory unit 25, multiplexer 26, address register 27, OR element 38. The first and second processors 23, 24 respectively comprise a processor element 28, 29, elements NOT 30, 31, elements OR 32, 33 and OR 34, 35, bus formers 36. 37.

As processor elements 28, 29, you can use single-chip microprocessors N1806 VM2 (6KO. 347.456 TU) with the system trunk MPI.

The memory unit 25 can be implemented on 537 RU9A chips, bus former 36, 37 on chips 530 AL2, multiplexer 26 on the basis of 533KP11 chips.

The device operates as follows. When the power is turned on, the processor elements 28, 29 generate the signals TSI 1, TSI 2, which, upon entering the corresponding installation bus of the initial state of the device 22, set the triggers 8, 9 to the O state, since the request buses ZP1, ZP2 of the device are set to zero potential, AND-NOT outputs 3, 4 are in state 1.

The first exchange synchronization signal OBM1, OBM2, received respectively through the first or second synchronization buses of device 22, will set triggers 1, 2, and 6, 7 to state 5, respectively. By setting potential 1 on the access ban buses of device 22 (signals BD1, BD2), the access of processors 23.24 to the memory unit 25 is blocked.

10 Device 22 provides each processor 23, 24 with two operating modes with a common memory unit 25 (regardless of the operating mode of another processor) - the first or second mode. If it is necessary to exchange arrays, one of the processors sets the first mode of operation with the device 22, which makes it possible to capture the shared memory 25 for two consecutive accesses by this processor. In the second mode 20, the device 22 provides the processors 23, 24 with the capture of the main memory trunk 25 for only one access. In this case, both in the first and in the second modes, a temporary separation of requests for access to the shared memory block 25 is carried out.

The mode of operation of the device is determined respectively by the state of the triggers 12, 13.

0 For operation in the first mode, the processor (for example, 23), sets the address of trigger 12 on the first bus address AD1 of device 22, which is for processor 23 a single-bit program-accessible (by record) register connected to the address / data highway .

The address decoder 18 decrypts the address set at its inputs and outputs a level 1 signal. After that, 0 on the first bus for synchronizing the exchange of device 22, the processor generates an OBM1 signal, which sets trigger 16 to state 1. Then, processor 23 removes AD1 from the highway the address and sets on potential 5 connected to the D-input of trigger 12 of the AD1 trunk line potential 1. Following this, the processor sets the signal DZP1, which sets trigger 12 to state 1 on the first data bus through the I14 element,

If it is necessary to synchronize the exchange of arrays, the second processor 24, similarly to the first, generates the corresponding sequence of signals and sets trigger 5 to state 1.

The request signal (RF1) set by the first processor 23 via the first request bus of the device 22 allows the frequency pulse F1 of the two-phase pulse generator 5 to set trigger 1 through the AND-NOT 3 element

to state T. When potential О is installed on the first bus of access prohibition (BD1), the memory access blocking is removed and the device 22 provides exclusive use of the memory block 25 by the first processor 23. At the same time, the multiplexer 26 allows passage to the address register 27 and the memory block These are 25 control signals from the outputs of the processor 23.

In this case, the NAND 4 element will be covered by the potential from the inverse output of trigger 1. The leading edge of the clock pulse TY1 of the processor element 28 sets the trigger 2 to state 1 on the first clock bus of the device 22, due to which the exchange resolution bus of the device 22 appears on the first signal P01, level O of which allows the processor 23 to continue the exchange procedure. The processor element 28 removes the request signal ZP1 and at the same time sets the address / data AD1 to the highway, which on the trailing edge (transition from potential 1 to potential O) of the OBM1 exchange synchronization signal is fixed in address register 27. With the same signal, trigger 2 is returned to the original state O. Earlier, when the request signal ZP1 of the first processor 23 is removed (transition from potential 1 to potential O), trigger 8 is set to state G1 through the AND-NOT 20 element, and blocking level O will arrive at its fourth from its inverse output th input NAND 4.

If the processor23 implements the procedure of reading data from the memory unit 25, it exposes the signal RHT1, which through the element 30 and the OR elements 32,33 opens the bus driver 36 to transfer information from the memory unit 25 to the address / data AD buses of the processor element 28. The same signal, coming through the multiplexer 26 and the OR element 38 to the enable input of the memory unit 25, transfers its outputs from the high impedance state to the actual state.

If the processor 23 performs the procedure of writing data to the memory unit 25, the processor element 28 exposes information on the AD buses and then generates a signal DZP1, which through the open multiplexer 26 sets the potential O (recording mode) at the control input of the memory unit 25. The same signal through the OR element 38 is fed to the enable input of the memory unit 25.

At the end of the exchange procedure of the first processor 23 with the memory unit 25 (the end of the first access), the signal level OBM1 changes from O to T, and trigger 1 goes into the initial state O. In this case, the NAND 4 element remains closed potential O s trigger 8 inverse output. Therefore, upon receipt of the second processor 24, the request signal ZP2 until the second call of the first processor 23 to the shared memory block 25 ends, the second processor 24 will not get access to the block 25. The possibility of such access

0 is only saved for the first processor 23.

When it is accessed the memory block 25 for the second time, the processor element 28 will set the signal ZP1 of the 1st level, which will set a trigger through the open AND-NOT 10 element 5

12c, the initial state is O, transferring the device 22 to the second operating mode.

The frequency pulse 1 of the two-phase pulse generator 5 through the NAND 3 element sets the trigger 1 to state 1, allowing access to the memory unit 25 to the first processor 23. On the leading edge of the clock pulse TI1, trigger 2 is set to state 1. Having received an enable signal

5 exchange P01. the processor element 28 removes the request signal ZP1 and sets the address / data address on the highway, and then the OBM1 exchange synchronization signal, which will return trigger 2 to its original state

0 O.T.K. If triggers 1 and 12 are respectively in state 1 and О, then when signal ЗП1 is removed (transition from potential Г to potential О), trigger 8 will be set to its initial state О. When the procedure for accessing block 25 is completed, processor 23 will pick up the signal OBM1 (transition from potential O to potential 1) and sets trigger 1 to the initial state O. Thus, if at this point in time the request signal ZP2 of the second processor 24 has been set, it will gain access to the common memory block 25. The first pulse frequency F2 shifted by half the period relative to the hour fota F1, set trigger b to

5 1, thereby closing the AND-NOT element 3, as well as the access of the processor 23 to block 25. When the processor element 29 receives the P02 exchange enable signal, it starts similarly to the processor element 28 to perform the exchange procedure with the memory 25, depending on the state of the trigger 13, the exchange will be carried out either in the first mode (two consecutive calls) or in the second mode (one turn).

If necessary, start work immediately from the second mode, the processors 23,24 must set the triggers 12, respectively

13 is similar to that described previously in state O. After this, the procedure for capturing the shared memory block 25 will be carried out similarly to the above, with the difference that after completing the exchange with the block 25 of one of the processors, the other gets the opportunity to immediately access the shared memory block 25. Triggers 8, 9 in this mode, due to the presence of potentials O on their D-inputs, will always be in the initial state O.

Due to the fact that the processors independently determine their own mode of operation with device 22. The following cases are possible: the device operates simultaneously with both processors in either the first or the second mode; the device works with the first processor in the first mode, and with the second processor in the second, or vice versa. The combination of modes may vary depending on the tasks to be solved by the particular control system in which the device 22 is included.

For example, let a certain area be allocated in the general memory block for an array of information, which is prepared by the first processor and processed as the second processor as it is completely updated. Before updating the information array, the first processor 23 sets the trigger 12 to state 1, thereby setting the first operation mode of the device 22 with this processor. With the second processor 24, the device 22 at this time works, for example, in the second mode. {Trigger 13 is in state O). The first processor, accessing the shared memory block, captures the shared memory trunk for two accesses. At the first of them, he analyzes the receipt in the mailbox of the states of the specified array and, when access is allowed to it, sets the receipt that prohibits the second processor from accessing the information array. With the same treatment, the appearance of the signal ZP1 causes the trigger 12 to be set to state 1. That is, the device 22 proceeds to work with the first processor in the second mode.

If it is necessary to read the indicated array by the second processor, it sets the trigger 13 to state 1, thereby putting the operation of the device 22 with it into the first mode. Then, when accessing the shared memory, the second processor captures it into two calls, in the first of which it analyzes the receipt in the mailbox of messages of the specified array. If the first processor has not yet completed updating the information, then the receipt indicates that access to

array to the second processor. In this case, the second processor performs another access to the shared memory, for example, reading an arbitrary memory cell, which is necessary

5 to reset the trigger 13 to the state O through the open element И Н Н Е 11. The indicated sequence of actions of the second processor will be performed until the receipt indicates permission to access the array, i.e. to complete the update of the array information by the first processor.

If the first processor for the array update is updated, then the analysis of the receipt at

On the 15th first access of the second to the shared memory, it will indicate permission to access the array. In this case, on the next call, the second processor will establish a receipt prohibiting access to the first processor

0 to the array. With the same treatment, the trigger 13 will be set in a state to transfer the further operation of the device 22 with the second processor to the second mode.

The presented example of one of the possible organizations for operating the claimed device in the system shows its ability to work independently with each of the processors in one of the previously described modes.

0 Thus, the capture of a common memory block into two consecutive accesses by each of the two processors independently allows synchronizing the access of processors to the common memory block

5 when exchanging arrays.

Claims (1)

SUMMARY OF THE INVENTION A device for accessing two processors to a common memory unit, comprising 0 eight triggers, two AND elements, two address decoders, two AND elements, a pulse generator, the inputs of the first and second decoders connected to the first and second bus address of the device respectively, the outputs of the first and second address decoders are connected respectively to the data inputs of the first and second triggers whose outputs are connected respectively to the first inputs of the first 0 and the second elements And, the second inputs of which are connected respectively to the first and second buses of the device record, the inverse inputs of the third and fourth triggers are connected respectively to the first and second buses of the exchange resolution of the device, the clock inputs of the first and second triggers are connected respectively to the first and second buses device synchronization, the outputs of the first and second elements are NOT connected respectively with installation inputs of the fifth and sixth flip-flops, characterized in that, in order to expand the scope of use, the ninth and tenth flip-flops are introduced into the device, from the third to the sixth AND-NOT elements, and the direct outputs of the fifth and sixth flip-flops are connected respectively to the data input of the third and fourth triggers and with the first input of the third and fourth AND-NOT elements, the second inputs of which are connected respectively to the first and second bus request devices and the first inputs of the first, second and fifth, sixth AND-NOT elements, second the input inputs of which are connected respectively with the first and second outputs of the pulse generator and the direct outputs of the seventh and eighth triggers, the inverse outputs of which are connected respectively with the third inputs of the second and first elements AND, the fourth inputs of which are connected respectively with the inverse outputs of the fifth and sixth triggers and with the first and second bus barriers to access the device, the sync inputs of the fifth and sixth triggers, combined with the reset inputs of the third and fourth triggers, respectively, are connected to the first and second synchronization bus exchanging the device, respectively, the clock inputs of the third and fourth triggers are connected respectively to the first and second clock buses of the device, the reset inputs of the seventh and eighth triggers are connected to the first and second buses of the device installation, the data inputs of the fifth and sixth triggers are connected to the zero potential bus of the device, the outputs of the third and fourth elements are NOT connected respectively, with clock inputs of the seventh and eighth triggers, the data inputs of which are connected respectively to the direct outputs of the ninth and tenth triggers, the data inputs of the clock and reset inputs of which are connected respectively to the discharge of the first and second bus address of the device, the outputs of the first and second elements AND, outputs of the first and sixth elements AND NOT.