SU1566360A1 - Device for interfacing two truncks - Google Patents

Abstract

The invention relates to computing and is intended for use in multi-machine and multi-processor computing systems. The purpose of the invention is to increase the speed of information exchange due to the ability to service requests from two highways in one cycle. The device contains a memory block 1, address registers 2, 3, switches 4, 5, decoders 6, 7, groups of elements AND 8, 9, D-triggers 10, 11, generator of 12 pulses, element HE 13, elements AND 14-19 , elements AND-NOT 20-23, RS-triggers 24, 25, elements OR 26, 27, buffer registers 28, 29. 1 Il.

Description

The invention relates to computer technology and can be used in multi-machine and multiprocessor computing systems. $

The aim of the invention is higher. the speed of information exchange due to the possibility of servicing requests from two highways in one cycle. 10

The device during the cycle of exchange of the highway allows you to serve requests from two highways. This is achieved by the fact that when a synchronization signal appears from the device’s memory block, the lock is removed from the installation of the second trigger request trigger. Thus, the total service time for simultaneous trunk requests is reduced. 20

The drawing shows a block diagram of a device.

The device contains a memory unit 1, two registers 2 and 3 addresses, two switches 4 and 5, two decoders 6 and 7, 25 two groups of elements And 8 and 9, two D-flip-flops 10 and 11, a pulse generator 12, an element NOT 13, six elements AND 14-19, four elements AND — NOT 20 - 23, two RS-flip-flops 24 and 25, two elements OR 26 and 27 and two buffer, registers 28 and 29. The device has the first 30 and second 31 address-information inputs - outputs, the first 32 and second 33 read inputs, the first 34 and second 35 write inputs, the first 36 and second 37 synchronization exchange inputs and the first 38 and second 39 response outputs.

The device operates as follows.

During operation of external devices (processors), address codes 36 are entered into address registers 2 and 3 at inputs 36 and 37. When an address appears that coincides with the address area of the memory block, for example, on register 2, the first decoder 6 generates a signal that goes to the information input of the first D-trigger 10. This signal is kept active for the duration of the exchange (equal to the duration of the Exchange signal) . The triggering of the first. D-trigger 10 occurs along the edge of the synchronization pulse. $

From the output of the first D-trigger 10 through the second element OR 27, the installation signal at 0, which prohibits the installation of the D-trigger 11 on the sync input, is input to the input at 0 of the second D-trigger 11. Locking of D-trigger 11 is supported until the first D-trigger 10 is set to 0. The first D-trigger 10 is set to 0 by the Response signal from the direct output of the first RS-trigger 24 .. through the first OR element 26.

The simultaneous operation of the D-flip-flops 10 and 11 is excluded, since at their sync inputs the signals from the generator 12 are inverse.

At the moment the first D-flip-flop 10 is triggered, the first switch 4 opens. If the Write signal is present at input 34, the switch 4 passes information from the first address — information input — output 30 to the input of memory block 1, and when the Read operation is performed, to the information input the first (second) buffer register 28. Information from the memory block 1 is recorded in the first buffer register 28 along the edge of the synchronization signal of the memory block, which through the element And 16 is fed to the second control input of the first buffer register 28.

The information output of the first (second) buffer register 28 (29) is connected to the address-information input-output 30 (31). The information recorded in the buffer register 28 or 29 is valid at the corresponding input – output during the time of the Read signal activity (inputs 32 and 33).

The address in the memory unit comes from the register 2 (3) addresses through a group of elements And 8 (9) under the control of the D-trigger 10 (11). Signals Read Write, which determine the operating mode of memory unit 1, comes through the elements And 14 (17) and 15 (18) also under the control of the D-trigger 10 (11). Element And 16 (19) controls the input of the synchronization signal from the memory (Response) to the installation input of the RS flip-flop 24 and the second control input of the corresponding buffer register 28 (29). From the output of the RS-trigger 24 (25), the Response signal through the AND-NOT 22 (23) element, provided that one of the inputs 32 (33) or 34 (35) is active, is sent to the output 38 (39) of the response of the first (second) trunk, RS-trigger 24. (25) is reset on the trailing edge of the Exchange signal (inputs 36 and 37).

When the interface device is accessed on two lines at the same time, the exchange of the second line with the device memory is delayed until the first D trigger is set to 0. When the D-flip-flop is set to 0, the information, address and control inputs of the memory block are disconnected from the first trunk and the interface device is ready to service the request of the second trunk.

From a comparative analysis of the invention and the prototype, it can be seen that the time taken for the device’s memory unit to service the trunk request for the prototype is longer by the time determined from the moment the Answer signal appears to the front of the next Exchange signal. From the description of the prototype, it follows that with constant access (for example, external devices) along one of the lines to the device, the latter is not released and there is no possibility to exchange on the other line. This can lead to a false conclusion about the unavailability of the address space zone allocated to the device: pairing interface.

Claims (1)

Claim A device for interfacing two highways, containing a memory unit, two address registers, two switches, two decoders, two groups of AND elements, two D-flip-flops, a pulse generator, an element NOT, six AND elements, the first information inputs and outputs of the switches connected respectively to the first and second address-information inputs / outputs of the device and to the information inputs of the first and second address registers, the second inputs and outputs of the switches are connected to the information input-output of the memory block, the outputs of the address registers and they are connected to the first inputs of the first and second groups of AND elements and the inputs of the first and second decoders, the output of the pulse generator is connected to the sync input of the first 11-trigger, and to the input of the element NOT, the output of which is connected to the sync input of the second II — trigger, information outputs D-flip-flops are connected to the outputs of the first and second decoders, the direct output of the first D-flip-flop is connected to the first inputs of the first, second and third AND elements, the second inputs of the AND elements of the first group and the first control input of the first switch, the direct output of the second D-trigger is connected to the first inputs of the fourth, fifth and sixth AND elements, the second inputs of the elements of the second group II and to the first control ed input of the second switch, the outputs of the first and second groups of elements AND are connected to the address input of the memory unit, the second inputs of the first and the fourth elements of And are connected to the second-input control inputs of the first and second switches respectively and are respectively the first and second read inputs of the device, the second inputs of the second and fifth elements of 20 And are respectively The first and second inputs of the recording device are connected to the third control inputs of the first and second switches, respectively, the outputs of the first and fourth 25th elements II are connected to the read input of the memory block, the outputs of the second and fifth elements of II are connected to the write input of the memory block, the output of the synchronization signal of which connected to the second inputs of the third and sixth elements AND, the sync input of the address registers are the corresponding synchronization inputs of the device’s exchange, characterized in that, in order to increase the speed and exchange information for the expense of the possibility of servicing requests from two highways in one cycle, it contains four NAND elements, two RS flip-flops, two OR elements, two buffer registers, the information inputs of which are connected to the information inputs of the first and second switches, the outputs of the first and second buffer registers are connected respectively to the first and second address-information inputs — outputs of the device, the first inputs of the first and second elements AND are NOT connected respectively to the first and second inputs of the recording The devices, the second inputs of the first and second elements AND are NOT respectively the first and second read inputs of the device, which are connected to the first read inputs of the first and second buffer registers, the outputs of the · the first and second elements are NOT connected respectively to the first inputs third and fourth elements Ί AND NOT, the outputs of which are respectively the first and second outputs of the device response, the outputs of the third and sixth elements AND are connected respectively to the installation inputs of the first and second RS-triggers and to the write inputs of the first and second buffer registers, respectively, the second read inputs of which are connected to bto -jq to the second inputs, respectively, of the third, its and fourth AND-NOT elements, to the direct outputs of the first and second RS-triggers, respectively, and to the first inputs of the first and second OR elements, respectively, whose second inputs are sub yucheny respectively to the direct outputs of the first and second D-flip-flops ,, IUGI element outputs are connected to inputs 0 installation in respective D-flip-flops, setting inputs to the first and second O RS-flip-flops are connected to respective inputs of a synchronization device exchange.