SU1417651A1 - Microprocessor monitoring system - Google Patents

Abstract

The invention relates to computing and can be used in microprocessor computing systems and control systems. The purpose of the invention is to increase the reliability of the microprocessor system by ensuring constant monitoring of its component regardless of the load on the main program. MiK- 26

Description

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srig.1

The processor system contains the first microprocessor 1, which executes the main program in the system, and connected to the buses of the internal highway 26 through the first state register 2, the first driver of the control signals 3, the transceivers 4 and 6, and the bi-directional transceiver 5, the Second microprocessor 9, executes who c. the system of the program for monitoring and diagnostics of its components is connected via the second status register 10, the second driver of the control signals 11, the transceiver 13, the bi-directional transceiver 12 to the local bus 21, 22, 23 buses and the transceivers 18, 20 and the bi-directional transceiver 19- tires internal device 26 Monitoring and diagnostic programs, as well as intermediate results of microprocessor 9, are stored in local constant 14 and real time 15 storage devices, while the operation modes and address modification are controlled by register 16 and address decoder 17. The operation of each of microprocessors 1 and 9 is synchronized with generator 7. The operation of microprocessors 1 and 9 on the internal highway 26 controls the arbiter unit of the internal highway 24, and the work on the external highway 32, to which the system is connected via transceivers. 27, 28 and a bi-directional transceiver 29, - block capture line 8 and the switch 25, through a line of interface signals; completion of operation 30, synchronization 31, access request 33, permission of priority access 34 and employment 35. 1C.p. f-ly, 6 ill.

one

The invention relates to computing and can be used in microprocessor computing systems and control systems.

The purpose of the invention is to increase the reliability of the microprocessor system by ensuring that its components are continuously monitored, regardless of the workload of the main program.

Fig. 1 shows a block diagram of a microprocessor system with built-in control $ in Fig. 2 is a block diagram of the arbiter of the internal highway; FIG. 3 is a time diagram of the operation of the internal highway arbiter unit} in FIG. 4, a block diagram of the system operation; FIG. 3 is a diagram of driver control signal drivers; figure 6 is a diagram of the block capture line

The device (Fig. 1) contains the first Microprocessor 1, the first state register 2, the first driver of the control signals 3, the first transceiver 4, the first bidirectional transceiver 5, the second transceiver 6, the clock generator 7,

-

block capture line 8, the second microprocessor 9, the second state register H, the second driver control signals 11, the second bidirectional transceiver. 12, a third transceiver 13, a local permanent memory (ROM) 14, a local random access memory (RAM) 15, a register 16, a decoder 17, a fourth transceiver 18, a third bi-directional transceiver 19, a fifth transceiver 20, a local address bus 21 , local data bus 22, local control bus 23, arbitration unit of the internal highway 24, switch 25, internal bus 26, with the test transceiver 27, seventh transceiver 28, fourth two-directional transceiver 29, input 30 complete neither the system operation, the external synchronization system input 31, the external trunk bus 32, the access request output 33, the priority access input 34, the signal input / output 35, the external mains occupancy: system hinges, the first 36 and second 37 inputs of the internal request, input 38 reset, request output 39, resolution input 40

- lA

access, the first 41 and second 42 PIDs, the first 43 and second 44 resolution outputs, the first 45 and second 46 outputs of the internal highway arbiter block.

The arbiter unit of the internal highway (figure 2) contains the first 47, the second 48, the third 49 and the fourth 50 tch igger, the first 51, the second 52 and the third 53 elements OR, the first 54, the second 55, the third 56 and the fourth 57 elements And, the first 58 and second 59 elements NOT, EXT 2, OR-NOT 60

The first and second control signal drivers (Fig. 5) contain a trigger 61, two switches 62 and 63, seven elements NOT 64-70, four elements AND 71-74, two elements OR 75 and 76. In the diagram (Figure 5) the inputs and outputs are indicated by the positions corresponding to those in FIG. 1, with the positions without brackets denote the inputs (outputs) of the first driver 3, and the positions in brackets denote the inputs (outputs) of the second driver 1J.

The block for capturing the line (Fig. 6) contains two triggers 77 and 78, five elements NOT 79-83, two elements OR 84 and 85, two elements 86 and 87.

The difference between shapers 3 and 11 is that the shaper 3 does not use the outputs MO (12), RD (14), WR (15,16) and the ADRF input, which is in jumper 3, a jumper 2-3 is set, and in the shaper 11 - jumper 1-2.

The device works as follows.

The first microprocessor 1 of the system executes the functions of the main processor in the microprocessor system, i.e. it executes the main program which is located in the system module of the ROM. Microprocessor 1 connects to address buses of external highway 32 via transceiver 4, address bus of internal highway 26 and transceiver 27, Microprocessor 1 connects to data lines of external highway 32 via bi-directional transceiver 5, duny bus of internal highway 26 and bi-directional transceiver 29, and bidirectional transceivers 29 and 29 are permanently enabled for information transfer, and are switched to receive only when executing memory read or input operations. To control tires

five

fv4

The main line 3., the content (it is a line of memory, memory, input and output reading memory loops, a microprocessor 1 J. The transceiver 6 is connected, the control bus is connected to the highway 26 and the transceiver 28. The signals on the control bus are formed by the microprocessor one

0 operations on the external highway 32 by the first driver of the control signals 3, the group of permitting inputs of which is connected to the outputs of the control signal of the microprocessor 1,

5 and a group of information inputs to the outputs of the state register 2, in which the state information at the beginning of the cycle is entered from the data bus of the microprocessor 1. one

The second microprocessor 9 of the device performs the functions of monitoring and diagnosing all the devices of the microprocessor system during operation of the microprocessor 1. To the address busses of the external highway 32, the microprocessor 9 is connected via the transceiver 13, the local address bus 21, the transceiver 18, the address bus of the internal highway 26 and transceiver 27, and a distinctive feature of this connection is that all the local address bus lines 21 are connected to the inputs of transceiver 18, except for the older one

5 bit address. The first bit of the register 16 is connected to the high-order input of the transceiver 18. Such a connection allows the external memory address to be modified when the microprocessor 9 is operating on the external highway 32. The microprocessor 9 is connected to the data buses of the external highway 32 via the bi-directional transceiver 12 local data bus 22, bidirectional transceiver 29, with bidirectional transceivers 12 and 19 also permanently included in the transmission of information. Microprocessor 9 connects to external control buses 32 via local control bus 23, transceiver 20, control bus of internal highway 26 and transceiver 28. Signals on control bus 23 when the microprocessor 9 accesses external trunk devices 32 are formed by a second driver control signals 11, the group allowing the input

0

flOB is connected to the corresponding control outputs of the microprocessor 9, and a group of informational inputs to the outputs of the second state register

10, the inputs of which are connected to the microprocessor data bus 9,

The transmission direction of the bi-directional transceiver 29 is determined by the output state of the switch 25, and the transmission direction of the bi-directional transceivers 5, 12 and 19 by the signals from the corresponding outputs of the first 2 and second 11 drivers of control signals

Local addresses 14, data 21 of microprocessor 9 are also connected to local ROM 14, which contains working programs of microprocessor 9, local RAM 15, which serves for storing intermediate information and register 16. Sampling signals from local ROM 14 and RAM 15 and register 16 are formed by the address decoder 17, and the control signals are generated by the driver of the control signals

11, and in this device the access to the register 16 is made as in a memory cell.

The address space of microprocessor-30 of highway 32 via line 33 is a low-level request signal. If the trunk is not busy and a higher priority device is required, input 34 receives a priority level low-level access enable signal that allows the device to capture the external highway 32. In the presence of a single level at the input-output 35 of the device, the block capture line 8

Sora 9 is distributed as follows. The entire I / O address area is completely related to I / O devices operating on the external line 32, i.e., completely coincides with the I / O address area of the microprocessor 1. The memory address space is divided in half, and the address space is pro ™

35

low level dew If the trunk is not busy and a higher priority device is required, input 34 receives a priority level low-level access enable signal that allows the device to capture the external highway 32. In the presence of a single level at the input-output 35 of the device, the block capture line 8

the space belongs to the local memory -40 which produces the resolution signals

ti 14, 15, 16j and the top - to the external memory. Physical separation of the address space of the memory is carried out using the high-order line of the local address bus address 21, 5 which is connected to one of the inputs of the control signal generator 11 and the resolution input of the decoder 17, and at zero signal level on this line the local address is addressed m 14 and 15 and register 16, and at a high level - external memory. In order to ensure that the microprocessor 9 can address all external memory in the device;

50

control inputs of transceivers 27 and 28 and bidirectional transceiver 29, transfer their outputs from the high-impedance state to the working one and simultaneously set the level of the external highway 32 (device input-output 35) to the level of the logical O external line 32. Access by microprocessors 1 and 9 to external line 26. controls the block of the internal line 2 arbiter, which operates as follows.

The signals initializing the possibility of modifying the address of the arbiter block of the internal magnet on the transceiver 18 are considered. The level of the signal coming from the first output of the register 16 to the input of the senior

17 () 516

bit transceiver 18, - defines the region of the address space of the external memory with which it operates. a microprocessor 9, wherein the logic level O at this input allows to address the lower region, and the logic level 1 - the upper region. .

0 Thus, microprocessor 9 can address any cell of external memory and any register of I / O devices connected to external trunk 32, and then use the lower half of the address space for accessing local memory 14 and 15 and register 16. This connection allows It avoids the cost of system memory resources for storing 20 programs for monitoring and diagnosing a system device.

The device is connected to an external highway 32 by controlling a block for capturing highway 8, which operates 25 Cfi in accordance with the protocols of the standard interface AND 41. If it is necessary to access resources of the external highway 32, the device generates and sends to the external arbiter

15

highway 32 on line 33 zap signal

low level dew If the trunk is not busy and a higher priority device is required, input 34 receives a priority level low-level access enable signal that allows the device to capture the external highway 32. In the presence of a single level at the input-output 35 of the device, the block capture line 8

Makes resolution signals

control inputs of transceivers 27 and 28 and bidirectional transceiver 29, transfer their outputs from the high-impedance state to the working one and simultaneously set the level of the external highway 32 (device input-output 35) to the level of the logical O external line 32. Access by microprocessors 1 and 9 to external line 26. controls the block of the internal line 2 arbiter, which operates as follows.

The signals that initialize the operation of the internal magnet 2 arbiter unit are internal

request incoming inputs 36

and 37 from the first 3 and second 11 for-

worlds of control signals. The internal request signals arrive at the information inputs of the flip-flops 47 and 48, to the syncroscopic inputs of which, via the element 56, signals come from the synchronization line 31, and to the synchronous input of the trigger 47 this signal enters through the element 58. Such activation allows you to avoid confusing situations the arbiter unit, internal highway 2, when requests on lines 36 and 37 arrive at the same time. At the same time, if the signals on

Lines 36 and 37 appear between the front-to-front and the device was previously produced.

20

25

thirty

synchronization signal, then only one of the triggers 48 and 49 switches on the next front of this signal, depending on which front has come at the moment (front or rear); if an internal request arrives only on one of the lines 36 or 37, then only three corresponding to this line are switched: - ger.

1 & certainty suppose that trigger 47 was switched, i.e. access to resources of external trunk 3-2 was requested by microprocessor 1. In this case, the signal from the direct output of the trigger 47 will go to the first input of the ground OR 52, at the output of which a signal arrives at the R input of the trigger 48 and prohibits its switching, to the inputs of the transceiver 4, 5, 6i preparing them 35 for switching on to the internal highway 26, to the first input of the element OR 53, from the output of which this signal goes - to one input of the And 57 element and to one of the inputs of the block for capturing line 8. Passage through the circuit of capturing the line 8, the microprocessor request signal 1 as an access request signal set The device arrives at the exit from there to the arbiter of the external highway 32. In this case, the device takes priority of the external highway 32 with the help of the block of capture of the highway 8, as described above. .50

After the capture unit 8 establishes a busy signal at input-output 35, the same signal (only high level) is set at input 40 of the arbiter unit of internal 55 trunk 2. The difference between these signals is only that on line 35 busy signal can be set40

then switching the output of the AND element in the state of logical 1 immediately after the output signal the OR 53 element. The high level signal from the AND 57 element stroke, arriving at the I input of the trigger 49, creates a logical combination 11 at its formation inputs, according to The clock signal coming from the output of the element NOT 59 to the synchronous input, the trigger 49 switches to the opposite state, i.e. Into logical logic 1. Signal c in the course of trigger 49, arriving at the input of the resolution of transceivers 4 and transfer them from a high-impedance state to a working one. In this case, the micro processor 1 gains access to the res itself of the external highway 32. At the same time, the same signal goes to the 1 input of the trigger 50, creating logical information on the information inputs on Bin 10, since the low level at the K input was set earlier from input 36 through element 2I-OR-NOT 60. At the same time, due to the rear signal of the bus synchronization, the output of the trigger 50 will be set to logical 1. The time interval between the switchings of the trigger 49 and 50 will be equal to the duration of the bus synchronization imp. The signal from the direct output of the trigger 50 enters the transceiver's enable input and translates it from the viewpoint impedance into the operational one, microprocess 1 provides access to the resources of the external highway 32 via the control unit. The signal from the inverse output of the trigger 50 is fed to the K input of the trigger 49 creating an information combination of its input 10, with which the trigger 49, with the arrival of the next signals from the synchronization line

flax by any admitter of the microprocessor system, and on line 40 - only by this device. The signal from the access permission input 40 is fed to another input of the And 57 element, causing its output to switch to the logical 1 state. It should be noted that if by the moment the request signal arrives from the OR 53 output, the And 57 element input on line 40 is received by the line capture unit 8 logical level 1 has already been set, i.e. seizure of the external highway 32

0

five

0

50

0

then switching the output of the element And 57 in the state of logical 1 immediately after the signal from the output of the element OR 53. The high level signal from the output of the element And 57 arriving at the I input of the trigger 49 creates at its information inputs a logical combination 11, in accordance with which, according to the sync signal coming from the output of the element NOT 59 to the synchronous input, the trigger 49 switches to the opposite state, i.e. in the logical state 1. The signal from the output of the trigger 49, arriving at the enable inputs of transceivers 4 and 5, will transfer them from the high-impedance state to the working state. At the same time, microprocessor 1 gains access to resources of external highway 32. At the same time, the same signal goes to the 1 input of trigger 50, creating a logical com -; - bin 10 on its information inputs, since the low level on the K input was previously set with the input 36 through the element 2I-OR-NOT 60. At the same time, on the falling edge of the signal, the bus synchronization, the output of the trigger 50 is set to the state of logical 1. Time interval. between switches triggers 49 and 50 will be equal to the bus sync pulse duration. The signal from the direct output of the trigger 50 is fed to the enable input of the transceiver 6 and translates it from the viewpoint impedance state into the working one, the microprocessor 1 gains access to the resources of the external highway 32 via the control unit. The signal from the inverted output of the trigger 50 is fed to the K input of the trigger 49, creating a logical combination 10 at its information inputs, at which the trigger 49, with the arrival of the following signals from the bus sync line

II “And

 31, remains in the state of logical 1, as well as on input of element 56, blocking the arrival of clock pulses. Triggers 47 and 48. Upon completion of the operation, input 30 of the device receives a signal to terminate operations from the subscriber who, through element 54, enters the readiness input of the control signal generator 3, where the readiness signal is input to the input of the microprocessor 1. The completion signal through the AND 55 element is blocked by the logic level from the trigger 48.

The microprocessor 1 completes the operation of accessing the resources of the external highway 32 and removes the signal from the input 36, The logic level O at the information input of the trigger does not change its state, since the input of the sync signals to its input is blocked in the element And 56, and at the input of the element 2I -Sh1I-NE 60 will change the state of the K-input of the trigger 50, set the level to logical 1. In accordance with the logical combination of the information inputs, the trigger 50 on the trailing edge of the sync pulse switches to the state of logical O, which Euodias transceiver 6 vysokoimpedans- Noe state. A high level from the inverse output of the trigger 50 unlocks the element And 56 and will create a logical combination 11 at the information inputs of the trigger 9,

The following sync pulse triggers 47 and 49 are switched to the logical O state. As a result, transceivers 4 and 5 are switched to a high impedance state by the resolution inputs and simultaneously from the sample inputs of the transceivers 4, 5, 6, the sampling signal is removed, the information inputs of the triggers 49 and 50 logical combinations 01 are set, prohibiting their switching upon receipt of the following clock pulses, and trigger 48 is unlocked on the input. At that, the cycle of accessing the resources of the external highway 32 to the microprocessor 1 ends, and the microprocessor 1 completes its cycle autonomously, performing 1 internal operations.

15

with jg

20

25

1763110

on the falling edge of the sync pulse of the bus that switched the trigger 47, the trigger 48 switches to the logical 1 state, while blocking the trigger 47 by the R input and preparing the transceivers 18, 19 and 20 on the sample inputs to turn on to the internal highway 26; Further, the circulation cycle of the microprocessor 9. to the resources of the external highway 32 occurs similarly to the cycle of the microprocessor 1. The efficiency of the microprocessor 1 and 9 in the microprocessor system is achieved due to the fact that the cycle of the external highway 32 is much less than the cycle of the microprocessor. For example, for the KP580IK80A microprocessor, the cycle is from 1.2 microseconds to 2.0 microseconds (excluding wait cycles), while the external trunk cycle usually does not exceed 300 not, and in many cases it is much less

In the system, each of the microprocessors 1 and 9, the preparation functions at the beginning of the cycle and the internal processing functions at the end of the cycle are autonomously executed, without occupying the internal highway 26 of the device and the external highway 32 of the system, which at these times can use the second microprocessor -, the action of microprocessors while

practically does not decrease. I After turning on the power or the general reset signal, the device centering 7 generates an initial setup signal that zeroes the internal registers of the microprocessors. 1 and 9, registers 2, 10 and 16, triggers 47, 48, 49 and 50, In this case, microprocessor 1 generates a call to the zero cell of the system ROM, and the microprocessor - to the zero cell of the local ROM 14, Microprocessor 1 starts to execute the main program of the system, microprocessor 9, independently of it, to the execution of programs for monitoring the system device.

 It should be noted that the control programs must be designed in such a way that during the control, information in the working registers of the I / O devices and in the system RAM is not distorted. To do this, special status registers can be provided for in the I / O devices, and when monitoring the system RAM, you can memorize

35

40

45

50

55

eleven

Simultaneously, the contents of the monitored cells in the local RAM, while taking into account that such monitoring is carried out over several cycles, it is necessary to suspend the operation of the microprocessor with 1 signal from the output of the register 16.

When an emergency situation is detected in any of the systems, the microprocessor 9, by writing the corresponding code in register 16, transfers the microprocessor 1 to the capture mode, and the system to the exclusive use mode of the trunk and performs a conditional transition to the diagnostic routine of the failed device, and depending on the results of diagnostics, it performs all the actions provided for in the system in case of an emergency.

Claims (1)

The formula of invention 1. Microprocessor system with built-in control, containing the first 25 microprocessor, second register thirty first microprocessor, first state register, first driver of control signals, first and second transceivers, first bi-directional transceiver, clock generator.or, line capture unit, local permanent memory, local random-access memory, and output address bus of the first the microprocessor is connected to the group of information inputs of the first transceiver, the bidirectional data bus of the first microprocessor is connected to the group of information inputs of the first the status register and the first group of information inputs-outputs of the first bidirectional transceiver, the input for selecting the transmission direction of which is connected to the output of the feature 40 states, the second driver of the control signals, the third through seventh transceivers, the second to the fourth bidirectional transceivers, the decoder, the register, the internal line arbiter unit and the switch, the clock input and the reset input of the second microprocessor are connected respectively to the synchronization outputs and initial setup of the clock generator, the output bus of the address of the second microprocessor is connected to the group of information and inputs of the third transceiver, a bidirectional data bus of the second mi the coprocessor is connected to the group of information inputs of the second state register and the first group of information inputs / outputs of the second bidirectional transceiver, the input the direction of the first view of the transmission direction; control signal gate, the output microprocessor control bus is connected to a group of resolution inputs — the first control signal generator, the output of the readiness attribute of which is connected to the ready input of the first microprocessor, the outputs of the first state register are connected to the rpyjinofi information inputs of the first control signal generator 55 the second register of the state of the co-signals, the group of interface control outputs of the first driver of the control signals is connected to connected to the first output of the transmission direction of the second control signal generator, the output control bus of the second microprocessor is connected to the permission input group of the first control signal generator, the output of the readiness attribute of which is connected to the input of the second microprocessor, is identical to the group of information inputs second shaper control signals, the group of outputs of the third ten 20 15 f, 51, 12 the group of information inputs of the second transceiver, the synchronization and initial settings of the clock generator are connected respectively to the clock input and the reset input of the first microprocessor, the first output of the line capture unit is the system access request output, the synchronization input of the line capture unit is connected to the priority access the line capture unit is the system access priority input, the line capture block input is the input house-busy signal output line external system, characterized in that, in order to increase the reliability of a microprocessor system by providing constant monitoring of its components independently of the main program load, it comprises a secondary states, second shaper of control signals, third to seventh transceivers, second to quarter bidirectional transceivers, decoder, register, internal trunk arbiter unit and switch, with the clock input and the reset input of the second microprocessor connected to the synchronization and initial outputs, respectively installation of the clock generator, the output bus address of the second microprocessor is connected to a group of information and inputs of the third transceiver, bi-directional data bus of the second mi the coprocessor is connected to the group of information inputs of the second state register and the first group of information inputs / outputs of the second bidirectional transceiver, the input the choice of transmission direction which moves of the second register of state connected to the first output of the transmission direction of the second control signal generator, the output control bus of the second microprocessor is connected to the group of resolution inputs of the first control signal generator, the output of the readiness attribute of which is connected to the input of the second microprocessor, bytes of the second register - dinene with a group of information inputs of the second driver control signals, a group of outputs of the third ir 141765 the transceiver is connected to the groups of information inputs of the fourth transceiver and the decoder, with groups of address inputs of the local permanent storage device and local random access memory, the group-interface control outputs of the second driver of the control signals are connected with the group of information inputs of the fifth transceiver , the output of the first register bit is connected to the higher bit input of the group of information inputs of the fourth transceiver, the output of the second pa The register view is connected to the capture input of the first microprocessor, the output of the third register register is connected to the installation input of the monopole mode of the trunk acquisition block, and the second group of information inputs and outputs of the second bi-directional transceiver is connected to the first information input group of the third bidirectional transceiver-with a group of information outputs of a local permanent storage device, with a dual-set JJ data bus of a local operational storage device OPERATION AND with inputs gruypoy Informatsionnye .kotorogo register reset input connected to the output of the clock generator initial installation, secondary. The second output of the sign of the direction of transmission of the second control signaling device is connected to the input selection of the direction of transmission of the third bidirectional transceiver and the first information input of the switch, the sampling inputs of the local permanent memory, the local operational memory and the register are connected respectively with the first, second and third outputs of the decoder, the output of the sign of the recording of the second control signal generator is connected to the recording inputs of the local operator active memory and register, the output of the read attribute of the second control signal generator is connected to the read input of the local storage device, the output of the upper bit of the output group of the third transceiver is connected to the pad input of the second control signal generator, the first and second inputs internal request block ap five Q „5 O. 5 0 5 11 t The internal trunk GjdTpa is connected to the outputs of the query mark of the first and second drivers for the I / signals, respectively. The reset input of the arbitrator of the internal trunk is connected to the output of the initial clock generator setting, you have the access code of the access block of the arbitrator the internal highway, the synchronization and termination inputs of which are connected respectively to the external synchronization input and to the system operation termination input, the inputs of the first and BTQporo transceivers and the first control input of the switch are connected to the first output of the arbitration unit of the internal trunk, a second output of which is connected to the inputs of the fourth and fifth transceivers, the third bidirectional transceiver and the second control input of the switch, the first and fourth permission inputs the transceivers and the first and third bidirectional transceivers are connected to the first output of the resolution of the internal trunk arbiter unit, the second output is allowed and which is connected to the enable inputs of the second and fifth transceivers, the request output of the internal line arbiter unit is connected to the request input of the line capture unit, the first and second readiness outputs of the internal line arbiter unit are connected to the ready inputs of the first and second control signaling devices, respectively the sign of the direction of transmission of the first shaper control signals connected to the second information input of the switch, the output of which is connected to the input selection direction In the transmission of the fourth bidirectional transceiver, the output groups of the first and fourth transceivers form a group of information inputs of the sixth transceiver, the output groups of the second and fifth transceivers form a group of information inputs of the seventh transceiver, the second group of information inputs and outputs of the first and third bi-directional transceivers form the first group of information inputs -outputs of the fourth two: 15 the directional transceiver, the enable inputs of the sixth and seventh transceivers, and the fourth bi-directional transceiver are connected to the output of the resolution of the line-grip block, the output groups of the sixth, seventh transceivers, and the second group of information inputs-outputs of the fourth bi-directional transceiver are the corresponding bus line by the blue- counter, one by one, one, one, one, one, one, one background, one, one, one, one, one, one background one, one background one, one line, one line, one line, 07, 08, 08, 08, 55, 56, 45, 45, 45, 45, 45 p. data bus system. 2, The microprocessor system according to claim 1, differs from the fact that the arbiter unit of the internal highway contains the first to the fourth triggers, three elements OR | the four elements AND, the bottom of the element NOT and the element 2И-OR-NOT, the first input of the internal request of the arbitration unit of the internal highway is connected to the D input of the first trigger and to the first input of the element 2I-OR-NOT, the R input of the first trigger is connected to the output the first element OR, the R input of the second trigger is connected to the output of the second element. OR, the reset input of the internal trunk arbitrator unit is connected to the first inputs of the first and second OR elements and the third and fourth trigger R inputs of the internal master The line is connected to the direct inputs of the first and second elements I, the output of the third element I is connected to the C input of the second trigger and through the first element NOT to the C input of the first trigger, the direct output of which is connected to the second input of the second element OR, the second the input of element 2I-OR-NOT, the first input of the third element OR, and is the first output of the arbitration block of the internal highway, inverted 10 15 20 1765116 The cHbft output of the first trigger is connected to the inverse input of the first element AND, the output of which is the first readiness output of the internal line arbiter unit, the direct output of the second trigger connected to the second input of the third element OR, the third input of element 2II-OR-NOT the second, input of the first element OR is the second output of the internal arbiter block selection, the inverse output of the second trigger is connected to the inverse input of the second element, the output of which is the second output of the internal arbiter trunk, the synchronization input of the internal trunk arbiter unit Connected to the first input of the third element I, to the C input of the fourth trigger and through the second element NOT to the C input of the third trigger, whose output is connected to the 1 input of the fourth trigger and is the first resolution output the arbiter of the internal highway whose second output resolution is connected to the forward output of the fourth trigger, the inverse output of which is connected to the K input of the third trigger and to the second input of the third element I, the second input of the internal the internal arbiter of the arbitrator of the internal highway is connected to the D-input of the second trigger and to the fourth TOi Tf input of the element 2I-OR-NOT, the output 35 of which is connected to the K-input of the fourth trigger, the output of the third element OR is connected to the first input of the fourth element AND and is the output of the request for the arbiter of the internal trunk line 40, the access enable input. connected to the second input of the fourth element And, the output of which is connected to the 1 input of the third trigger. 25 thirty hjy Job mpt Ctfgva / o) Jl Appeal by nilooomiaoresu to system. ROM The start is a dan. 1 infit No tires.  1 t not. 0) Kidan oazreshen -  Yes, Not Exchange with the resources of the External Master. chrealize / pack Job. MP9 With dual j Jl Appearance t zero address to the present ROM About. normal installation /standart cn / rorm on local tires. 21,22,23  one 0 throwing Exchange with resources, bnesh. highway but Joo / nff. - - Dumept / oL