SU1151975A1 - Memory control unit - Google Patents

Abstract

1. A DEVICE FOR CONTROL OF MEMORY, containing the first and second elements OR, trigger, regeneration address counter, regenerator row selector and clock generator, with the first input of the first element OR connected to the device reset input, trigger information input connected to the device synchronization input, output trigger is connected to the first input of the second OR element, the output group of the regeneration address counter is connected to the first group of information inputs of the regeneration row selector, the second group is inf The input inputs of which are connected to the group of address inputs of the device, the output group of the regenerator row selector is connected to the group of address outputs of the device, the output group of the tamper signal generator is connected to the output group of the device’s internal synchronization signals, the reset output at the end of the regeneration of the tactile signal generator is connected to the trigger reset input, Clock driver start input combined with regenerator address issuance enable input and se control input Regeneration line vector, characterized in that, in order to reduce power consumption, a frequency divider, an AND element and a comparator are entered into it, the resolution input of the frequency divider connected to the output of the first OR element, the second input of which is connected to the device blocking-readiness input, The first clock input of the frequency divider is connected to the first clock input of the device, the reset input of the frequency divider is connected to the trigger input, to the synchronization input of which is connected: 2 the synchronization control input (About va, the output of the frequency divider is connected to the second input of the second element OR, the output of which is connected to the first input of the element I, the output of which is connected to the enable input of the regeneration address counter, the enable input of the component commulator is connected to the trigger output, the first group of information inputs from the comparator connected to the output group of the regeneration address counter, O1 the second group of information inputs of the comparator is connected to the group of address inputs of the device, the output of the comparator is connected to the second input. And, the clock clock driver is the clock input of the device. 2, the apparatus according to claim 1, characterized in that the clock driver contains a shift register, a voltage level converter, an AND element, an elec

Description

ment OR, element NAND, and the reset input of the shift register is connected to the trigger input of the imager, the clock ah / od of which is connected to the synchronous input of the shift register, the outputs of the first, second, third and fourth bits of the shift register are connected to the first and second inputs of the , the OR or the element and the NAND, respectively, the output of the OR element is connected to the input of the level converter eg 1151

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and the first input of the AND element, the second input of which is connected to the output of the NAND element and the reset output at the end of regeneration, the group of outputs of the internal synchronization signal of the former, the outputs of the voltage level converter AND of the AND element are connected to the outputs of the selection and address gate of the output group internal synchronization signals shaper.

The invention relates to computing technology, in particular to microprocessor systems with dynamic RAM and can be used for debugging microcomputers with step-by-step operation.

A stand-alone controller for regenerating information of dynamic RAM for microprocessor systems is known, comprising a timer, an arbitrator, a row address selector, a regeneration address counter, a driver of control signals, buffers. With the approach of the moment of mandatory regeneration, the timer forms a request arriving at the arbitrator. Depending on the use of RAM, the request is satisfied by the arbiter either after the processor has finished the call or immediately. This fact through the row address selector allows the address of the next regenerated row generated by the counter to pass to the corresponding bits of the system address bus. At the same time, the driver of the control signals provides the signals to the RAM necessary for its regeneration. At the end of the regeneration cycle, the row selector restores the communication of the system address bus with the corresponding processor address bits; the content of the regeneration address counter is incremented by GL.

 The disadvantage of the autonomous regeneration controller is the need to suspend the microprocessor during the regeneration of information; This suspension, resulting in a decrease in performance, is produced by applying a inhibitory potential to the Ready Microprocessor line.

The closest to the proposed is a non-autonomous, re-generation controller containing a row address selector — a regeneration address counter, a control signal generator, 3J buffers. Activation of a non-autonomous regeneration controller is effected by the synchronization signal of the microprocessor, which gates the byte of the state in each machine cycle. Since the microprocessor cannot access the RAM at this time, the regeneration of the next line of the RAM produced by the synchronization signal is reliably resolved. with processor circulation. Thus, the Synchronization signal in a non-autonomous controller performs the role of a timer and arbiter of the autonomous regeneration controller, thereby eliminating the need to suspend the microprocessor.

The non-autonomous regeneration controller also provides backup activation in cases of no Synchronization signal, namely, when microprocessor i is in the Standby state and when the microprocessor system is generally reset. In these cases, the clock pulses F2 TTL, unconditionally generated in the presence of power, are the triggering ones.

The disadvantages of a non-autonomous regeneration controller are the excessive regeneration frequency, the AND drive (and the excessive power consumption. And the Inability to use it), the controller is in the Standby microprocessor systems state, including, for example, in debugging microcomputers, Step mode the microprocessor of the trash systems is accomplished by periodically blocking (supplying negative potential) the line of the microprocessor’s readiness, as a result of which it goes into standby mode, corresponding signal. Presence of a signal The waiting leads to the transition of a non-autonomous controller to the standby mode of regeneration cycles occurring in each tick of the state. Waiting with the arrival of the trailing edge of the system sf2 TTL sync pulse, inverse with respect to the system sync pulse F2. on the same front of F2 sync pulse, the microprocessor polls the Ready line in each state clock of the Wait so that when the Readiness signal on it is restored, start the next machine clock cycle TZ. During a TK cycle, information is usually exchanged between the microprocessor and the RAM. However, the next regeneration cycle, the duration of which is equal to the machine cycle of the microprocessor, begins at the end of its cycle of state O and sits before the cycle of the TOR and ends only at the end of the cycle of the TZ. There is a conflict situation when microprocessor access to RAM cannot be realized. The invention is a reduction in power consumption. The goal is achieved by the fact that the memory control device containing the first and second OR elements, the trigger, the regeneration address counter, the regeneration line selector and the clock generator, the first input of the first OR element is connected to the device reset input, the information input of the trigger is connected .to the device sync input, the trigger output is connected to the first input of the second element OR, the output group of the regeneration address counter is connected to the first group of information inputs of the row selector regeneration, the second group of informational inputs of which is connected to the group of address inputs of the device, group i of the outputs of the selector of the regeneration lines is connected to the group of address outputs of the device, the group of outputs of the clock generator is connected. to the group of outputs of the device's internal synchronization signals, the reset output at the end of regeneration of the clock generator is connected to the reset input of the trigger, the trigger input of the clock generator is combined with the enable input of the regeneration address counter and the input of the regeneration row selector, the frequency divider is entered, and and a comparator, wherein the resolution input of the frequency splitter is connected to the output of the first element OR, the second input of which is connected to the device readiness lock input, the second clock input of the frequency divider is connected to the first clock input of the device, the reset input of the frequency divider is connected to the trigger input, to the synchronization input of which the synchronization control input of the device is connected, the output of the frequency divider is connected to the second input of the second element OR whose VELSOD is connected to the first input of the element AND whose output is connected to the enable input of the regeneration address counter, the enable input of the comparator is connected to the trigger output, the first group of information inputs com Arathor connected to the group: O regeneration counter addresses, the second group of information inputs of the comparator is connected to the group address inputs of the device, the comparator output is connected to the second input of the AND gate, the clock shaper clock signals is the clock input of the device. In addition, the clock driver contains a shift register, a voltage level converter, an AND element, an OR element, an AND-HHO element, and the shift register reset input is connected to the start input of the shaper, whose clock input is connected to the shift register sync input, peo outputs.

The second, third and fourth bits of the shift register are connected to the first and second inputs of the OR element and the NAND element, respectively, the output of the OR element is connected to the input of the voltage level converter and the first input of the AND element, the second input of which is connected to the output of the NAND element and the reset output at the end of the regeneration, the group of output signals of the internal synchronization signal. The outputs of the voltage level converter and the AND element are connected to the outputs of the selection and the address gate of the output group of the internal signals enney synchronization shaper.

FIG. 1 is a block diagram of a memory management device; in fig. 2 - timing diagrams explaining the connection of the regeneration signals (Fig. 2i-k) with the time relationships of the microprocessor system (Fig. 2a-d); Fig. 3 is a block diagram of a clock clock generator and a timing diagram of its operation.

The device (Fig. I) contains the element OR 1, a divider 2 frequencies, a trigger 3, set by the front, an element OR 4, a counter of 5 registration addresses, a selector of 6 registration lines, a driver of contact signals 7 (for RAM based on K505RU1 microcircuits), And 8 and the comparator 9 The clock driver (Fig. 3A) consists of a shift register 10, the elements OR t1, AND-NO 12 AND 13 and the converter 14 with voltage equalizer.

The device receives signals from the microprocessor system based on the K580K80 microprocessor. The device is designed to ensure the regeneration of information in the usual (automatic) mode of microprocessor systems, as well as in the system reset and idle. A special case of the state of waiting. is a step mode operation of microprocessor systems.

The device works as follows.

In automatic mode, regeneration cycles can be started with the arrival of the synchronization signal from the microprocessor to the second input of the trigger 3. The installation of trigger 3, leading to the start of the regeneration cycle, does not occur in each machine cycle, but only in the first cycle of each command, due to the connection of the trigger synchronization input 3 with the state bit M1 indicating the microprocessor is in the first machine cycle. Due to the installation of flip-flop 3 through the elements of OR 4 and And 8, the selector 6 switches and enables passage to RAM of the address of the next regenerated line from the outputs of counter 5. Simultaneously, the shaper 7 of the clock signals, which are required for the RAM to operate in regeneration mode, is started. At the end of the cycle, at the output of the clock generator 7, a signal appears that resets the trigger 3, which in turn causes the switch 6 to switch back and the address is incremented at the outputs of the counter 5.

Since the information of those lines of RAM that the microprocessor is accessing is automatically regenerated, this circumstance is used to prohibit regeneration cycles in those cases when the line of RAM to which the microprocessor is going to be regenerated. As is known, the address of the RAM cell to which the microprocessor accesses in the first machine cycle — the instruction sampling cycle — is output to the address highway simultaneously with the active status word on the data highway (Fig. 2, g, e). In the proposed device, at the beginning of the first machine cycle, the lower six bits of the address provided by the microprocessor are compared with the shorthand address of the next regenerated line. The corresponding time ratios for address matching are shown in FIG. 2, and-l.

When the addresses of the address and regeneration lines match, the output potential of the comparator 9 appears at the first input of the element 8. This potential blocks the passage of the positive triggering potential of trigger 3 (Fig. 2,) through the elements OR 4 and 8 to counter 5, the selector 6 and j shaper 7 clock signals. Comparing the propagation delay of the signals of the comparator 9 and the elements OR 4 and I 8, we can say that the blocking of the triggering potential is somewhat delayed, as a result of which a narrow pulse appears at the output of the element And 8 (Fig. 2, l) instead of the full wide signal formed during no match of addresses. The appearance of a narrow pulse at the output of the AND 8 element is not sufficient for the selector 6 and shaper 7 to perform its functions during the regeneration cycle, since this requires the presence of a normal wide signal at the output of the AND 8 element 8 Therefore, the prepared regeneration cycle will not be implemented. At the end of the trailing edge of the pulse in element I B, the counter value 5 is incremented, therefore the addressing of the RAM lines for regeneration will not be violated, and the next line will be regenerated (if no addresses match) in the next regeneration cycle. As is known, for the regeneration of RAM based on K565RU1 microcircuits, a 12-volt resolution signal CE is sufficient for these microcircuits. When sequentially accessing all 64 rows of the chip matrix, the clock generator 7 (Fig. 1) generates a resolution signal and an address strobe signal, which provides the necessary time ratios of the resolution signal and the address of the regenerated line to the RAM from the output of the selector 6 (Fig. 1) With the beginning of the regeneration cycle, the first input (sequential input of information) of register 10 receives a logical 1 signal (from the output of the And 8 element, Fig. 1). The second input (syncro) of register 10 receives 20 MHz clock pulses (FIG. 3) Under the influence of these clock pulses, the outputs of register 10 will start sequentially switching to the logical 1 state (Fig. 36). A negative reset signal is generated at the output of the AND-IT element 12 supplied to the third input of trigger 3 (and divide l 2, fig. 1). Due to resetting flip-flop 3, the logical input O will start to be sent to the first input of the register (fig. Za), and the output of register 1 will start sequentially switch to this logical state 758 The output signal of the element OR 11, the passage through the converter 14, turns into a 12-volt resolution signal CE. The output signal of the element And 13 uses the given time gate of the address of the regenerated line that enters the RAM from the outputs of the selector 6 (FIG. 1). The prohibition of special regeneration cycles with the coincidence of addresses of addresses and regeyeration leads to additional savings in power consumption. However, the main savings achieved by the proposed device in automatic mode are achieved due to The existence of regeneration cycles is not in each, 1st machine cycle, as in the known device, but only in the first machine cycle of each command. Each K580K80 microprocessor command can contain from one to five. The specific frequency of regeneration of the proposed device is determined by which commands are included in this program. On average, in comparison with the automatic mode of the known device, the regeneration frequency is reduced by about 3 times. Modern dynamic RAMs are regenerated in 64, 128, or 256 regeneration cycles. The RAM requiring 64 cycles for full regeneration was regenerated with a lime device in 0.12-0.15 Vic with an acceptable regeneration period of 2 ms. The proposed device in the automatic mode of operation of microprocessor systems produces 64 cycles of regeneration (at) in 0.40-0.45 ms, 128 cycles (at) in 0.8-0.9 we, 256 cycles (at) in 1.6- 1.8-ms, which provides a significant reduction in power consumption. Consider the operation of the proposed memory management device Reset System and Standby. If there is one of the signals Reset the system or Lock ready (inversion of the Ready signal) with the arrival of the falling edge of the signal F2 TTL, the divider 2 frequencies are started. After a time interval determined by the frequency division factor, the output of divider 2 is a signal that triggers the regeneration cycle, similar to

but how it happens in automatic mode.

FIG. 2, k, the dotted line shows the time intervals during which regeneration cycles are possible when the proposed device is in the Idle state (the solid line in Fig. 2u shows the time interval during which the regeneration cycle is performed in automatic mode). Owing to the system signal, the readiness lock prevents the start of the regeneration cycle at the end of the last wait cycle before the microprocessor resumes execution of this command, as it was in the prototype (Fig. 2, a). Ta7510

By using a CMM, a possible conflict situation is excluded, and therefore the proposed device can be used in the Expectation state of microprocessor systems, including debugging devices with a step-by-step mode of operation.

Introducing a frequency divider instead of a trigger in a known device allows, in the System Reset and Waiting states, to perform a regeneration cycle with a period close to the allowable one, by not using the microprocessor-based clock frequency system as a regeneration frequency, which leads to a large power consumption of these states. them in known devices.

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Claims (2)

1. A MEMORY CONTROL DEVICE containing the first and second OR elements, a trigger, a regeneration address counter, a regeneration line selector and a clock generator, the first input of the first OR element connected to the reset input of the device, the information input of the trigger connected to the synchronization input of the device, output the trigger is connected to the first input of the second OR element, the group of outputs of the regeneration address counter is connected to the first group of information inputs of the regenerator row selector, the second group of information of the input inputs of which is connected to the group of address inputs of the device, the group of outputs of the selector of regeneration lines is connected to the group of address outputs of the device, the group of outputs of the driver of clock signals is connected to the group of outputs of the signals of internal synchronization of the device, the reset output at the end of the regeneration of the driver of clock signals is connected to the reset input of the trigger, the start input of the clock generator is combined with the enable input of the counter of regeneration addresses and the control input of the reg line selector non-operation, characterized in that, in order to reduce power consumption, a frequency divider, an AND element, and a comparator are introduced into it, and the resolution divider input is connected to the output of the first OR element, the second input of which is connected to the blocking input · device ready, the first clock input the frequency divider is connected to the first clock input of the device, the reset input of the frequency divider is connected to the input of the trigger, to the synchronization input of which the control synchronization input of the device is connected, the output of the frequency divider is connected to the second input of the second OR element, the output of which is connected to the first input of the And element, whose output is connected to the enable output of the regeneration address counter, the enable output of the comparator is connected to the trigger output, the first group of information inputs of the comparator is connected to the output group of the regeneration address counter, the second group of information inputs of the comparator is connected to the group of address inputs of the device, the output of the comparator is connected to the second input. element And, the clock input of the driver of clock signals is the clock input of the device. 2. The device according to claim 1, characterized in that the clock signal generator comprises a shift register, a voltage level converter, an AND element, an SU, 1151975 OR element, an NAND element, the shift register reset input being connected to the driver trigger input, clock input / one of which is connected to the sync input of the shift register, the outputs of the first, second, third and fourth bits of the shift register are connected to the first and second inputs of the element, OR element and AND-NOT element, respectively, the output of the OR element is connected to the input of the converter voltage levels and the first input of the AND element, the second input of which is connected to the output of the AND-NOT element and the reset output at the end of regeneration, the group of outputs of the internal synchronization signals of the driver, the outputs of the voltage level converter of the first element AND are connected to the selection and gate outputs of the address of the group of signal outputs shaper internal synchronization. \