SU1575190A1 - Device for controlling dynamic memory - Google Patents

Abstract

The invention relates to computing and can be used in computer memory management devices, in particular semiconductor dynamic memory, made on the LSI. The purpose of the invention is to simplify the device and increase its speed by reducing the average waiting time to satisfy an external request. The device contains a regeneration timer 1, a regeneration request trigger 2, a synchronization unit 3, a multiplexer 4 addresses, a regeneration address counter 5, AND 6 and 7 elements, an OR 8 element, an encoder 9, a register 10, a response trigger 11. 2 Il.

Description

The invention relates to computing and can be used in computer control devices, in particular, semiconductor dynamic memory, implemented on an LSI.

The purpose of the invention is to simplify the device and increase its speed by reducing the average waiting time to satisfy an external request.

Figure 1 shows the block diagram of the proposed device for managing dynamic memory; figure 2 - timing diagram of the device.

The device contains a timer 1 regeneration,; trigger request 2, regeneration, synchronization unit 3, multiplexer 4 addresses, regeneration address counter 5, AND 6 and 7 elements, OR element 8, encoder 9, register 10, response trigger P, read input 12, write input 13, a group of memory management outputs 14, a group of memory address outputs 15, a group of memory address inputs 16, a response signal output 17.

In the timing diagram (Fig. 2), all signals are conventionally shown of positive polarity. In this case, the following notation is taken on the diagram: clock input a register 10; external request signal b at input 12 of reading; information inputs in register 10, the signals of which vary depending on the presence of a particular request; signals g at the output of register 10; times e for which the synchronization unit 3 forms a memory access cycle on an external request or on request for the regeneration of the memory; a memory access signal e on external request at the third output of the synchronization unit; the signal w at the inverse output of the trigger 11, which is the response signal and arrives at the second inputs of the elements 6 and 7; signals from the direct output of trigger 2 of the request for regeneration; the signal and the end of the regeneration cycle at the second output of the synchronization unit 3.

The device works as follows.

An external read signal is an external request for organizing a data read cycle from the memory. External

0 5 0 5 Q

five

the write signal is an external request for organizing a cycle for writing data to the memory. The signal at the output of trigger 2 of the request for regeneration is a request for memory regeneration. In the initial state, in the absence of external requests and requests for memory regeneration, passive signal levels are present at the inputs of the encoder 9 and, accordingly, at its outputs, as well as at the information inputs of the register 10 and its outputs. The synchronization unit 3 generates signals only at its fourth output, which are polling signals arriving at the clock input of register 10. In this case, the trigger 11 is in the zero state, and level 1 is present at its inverse output.

The inputs of the elements 6 and 7 are so connected to the encoder 9 that they have a higher priority than its third input connected to the direct output of trigger 2 of the request for regeneration. The encoder 9 generates at the output a combination of signals corresponding to a signal at each input. If the first input (or the second, since they cannot be present simultaneously) sends the signal and the signal to the third, then the output of the encoder 9 will contain a combination of signals corresponding to the input signal at the first input.

When one of the external requests appear at the inputs 12 or 13 at the output of the corresponding element AND 6 or 7, a signal is received that, arriving at one of the inputs of the encoder 9, will cause at its output a corresponding signal combination that the inputs of register 10 will be fixed in it by a polling pulse coming from the fourth output of the synchronization unit 3 to the clock input of the register 10.

When signals appear at the output of the register 10 and respectively at the group of inputs of the request of the synchronization unit 3, the synchronization unit stops issuing polling signals and starts generating control signals for the address multiplexer 4 (at its first output) and memory, which are outputted at outputs 14 in according to the received request.

five

At the end of the memory access cycle, a signal at the end of the cycle is generated at the third output of synchronization unit 3, which is fed to the setup input of trigger P. At its inverse output, there is a response signal that goes to output 17 and to the second inputs of elements 6 and 7, prohibiting the passage of external signals to the input of the encoder 9. This is necessary so that the previous combination of signals corresponding to the satisfied request is not re-recorded in register 10, since after the end of cycle signal the synchronization unit 3 At its fourth output, the polling signals begin to form at the clock input of the register 10. When a request signal is removed from inputs 12 or 13, the output of the OR element 8 is a signal that, when it enters the reset input of trigger 11, sets it to a zero state in which the response signal from output 17 and the inhibit signal from the second inputs of the And 6 and 7 elements are removed.

When the regeneration timer 1, having generated a time interval, develops a short pulse at its output, this pulse arriving at the setup input sets the trigger 2 of the generation request to one state, and the signal from its inverse output goes to the third input of the encoder 9.

In the absence of external requests at inputs 12 and 13 at the output of the encoder, according to a Vits, a combination of signals corresponding to the request for memory regeneration. The synchronization unit 3 will generate the corresponding control signals of the multiplexer 4 addresses and memory and at the end of the cycle will generate a signal at its second output, which, arriving at the counting input of the regeneration address counter 5, will increase its content by one. At the same time, the third output of the synchronization unit 3 does not generate a signal, and the polling signal from its fourth output goes to the clock input of the register 10, and if the data combination does not change at the information inputs, then the memory regeneration cycle is repeated.

Work in this sequence continues until

ten

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the regeneration address counter 5 does not overflow; in this case, the second output of the counter shows the overflow signal that goes to

5, the reset input of trigger 2 of the request for regeneration sets it to the zero state, which removes the request for memory regeneration from the third input of the encoder and restarts the regeneration timer 1 again.

If an external request is registered in register 10, then the request for regeneration will be satisfied only after the completion of the started cycle. When the request for regeneration is set at the third input of the encoder 9, the incoming external request for the first or second input of the encoder will cancel the memory regeneration, since the external request has a higher priority, only after the completion of the started cycle.

On the timing diagram (figure 2)

25 that in spite of the presence of a request for regeneration, upon the appearance of an external request (e), it is satisfied with a minimum delay which is always less than the time of one regeneration cycle.

These collisions are possible only during the period of time allowed for registration and determined by the timer. The number of collisions depends on the intensity of the arrival of external requests. Due to the fact that the priority of the external request is higher than the request for registration, the average waiting time for the satisfaction of the external request is reduced.

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Claims (1)

The invention includes a device for managing dynamic memory containing a non-regeneration request trigger, a synchronization block, an address multiplexer, a regeneration address counter, and a group of its outputs connected to the first group of information inputs of an multiplexer address whose outputs are connected to the device’s memory address output group , the group of inputs of the memory address of which is connected to the second group of information inputs of the multiplexer of the address, the control input 55 of which is connected to the first output of the synchronization unit, the second output of which is connected to the counting input of the counter of the regeneration address, and the group of outputs of the synchronization unit of the connector 715 Not with a group of outputs for managing the memory of a device, characterized in that, in order to simplify the device and increase its speed, by reducing the average waiting time to satisfy an external request, the Regeneration Timer, the first and second elements AND, the OR element are entered into it. , encoder, register, response trigger, the first input of the first element AND is combined with the first input of the OR element and connected to the reading input of the device, the first input of the second element AND is combined, 4 with the second input of the OR element and connecting to the input record and devices, and the outputs of the first, second elements of the AND and the direct output of the request trigger regeneration are connected respectively | eight  , 0 with the first, second and third inputs of the encoder, the outputs of which are connected to the information inputs of the register, the outputs of the register are connected to the group of inputs of the request attribute of the synchronization unit, the third output of which is connected to the input of the response trigger installation, the fourth output to the clock input of the register, the reset input of the trigger response is connected to the output of the OR element, and the output of the response trigger is connected to the second inputs of the AND elements and to the output bus of the response signal, the finger output of the regeneration address counter is connected to the reset input of the trigger The time of request and with the input of the start of the regeneration timer, the output of which is connected to the input of the trigger installation of the request for regeneration. at & 38th L X r-t-g- RGI RGN, RGN RGN Well P 1C P Well 3 and P Compiled by A. Barkin - Editor Y. Sereda Tehred M. Khodanich Proofreader T. Malets Order 1786 Circulation 563 VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nab. 4/5 1C -% .. P l l -e Ql / lZ Subscription