SU1529239A1 - Priority arrangement for accessing common memory - Google Patents

Abstract

The invention relates to digital computing and is intended for use in multiprocessor systems based on microprocessors and microcomputers. The aim of the invention is to reduce hardware costs and expand functionality by quickly changing the sequence of processor access to shared memory. The device contains a pulse generator 1, a single pulse shaper 2, a pulse distributor 3, And 4, 5, 6, and 7 elements, an address decoder 8, a reading register 9, a write register 10, a trigger 11, bus drivers 12, 13, 14 and 15 , prohibition circuit 16 for read signal bus 17, prohibition circuit 18 for write signal bus 19, prohibition circuit 20 for read information signal bus 21, prohibition circuit 22 for write information bus 23, prohibition circuit 24 for address bus 25, priority register 26c information input 27 and record input 28, setup / reset input / 30 and the counter 31 count input distributor 3 pulses. 2 Il.

Description

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changes in the processor access to the shared memory. The device contains a pulse generator 1, a single pulse shaper 2, a pulse distributor 3, And 4, 5, 6. and 7 elements, an address decoder 8, a reading register 9, a write register 10, a trigger 11, bus drivers 12, 13, 14 and 15 , prohibition circuit 16 for read signal bus 17, prohibition circuit 8 for write signal bus 19, prohibition circuit 20 for read information signal bus 21, prohibition circuit 22 for write information bus 23, prohibition circuit 24 for address bus 25, register 26-priority with information input 27 and input entry 28, entry 30 of the initial installation ( reset) and the counting input 31 of the distributor counter 3 pulses. 2 Il.

The invention relates to digital computing and is intended for use in multiprocessor systems based on microprocessors (MPs) and microcomputers.

The purpose of the invention is to reduce hardware costs and expand functionality by quickly changing the sequence of processor access to shared memory.

Fig, 1 shows a functional diagram of the device; figure 2 - timing charts of his work.

The device (figl) contains a generator 7 of pulses 1, a generator of 2 single pulses, a distributor of 3 pulses, elements 4-7, an address decoder 8, a reading register 9, a register 10 recording, trigger 11 ,, bus drivers, prohibition schemes 16 read signal bus 17, interdiction circuit 18 for write signal bus 9, ban 20 for read 2 bus, read ban circuit 22 for written information bus 23, ban ban 24 for address bus 25, priority register 26, its information input 27 and input 28 records, outputs, 29 pulse distributor, input 30 start oh on stopping discharge) pulse distributor counter and the count input 31 of the counter 3 u shulsov distributor.

The device works as follows about

Upon receipt of a reset signal at input 30, the pulse distributor counter goes to the zero state. The clock pulses of the generator 1 from the Output 32 receive the inputs of the GSH, providing the clocking connected to the common memory No.. At the end of the initial signal, the next pulse generator from the output

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Generator 1 causes the appearance of unity) 1 in the counter of the distributor of 3 pulses at the input. 3 5 a at input 28 allows entry in register 26 of the priority code at input 27.

The operation of the pulse distributor on the three outputs can be represented as. three equations for Y g – s, which correspond to the structure of a pulse distributor combinational circuit. The first three bits indicate (contents) the state of register 26, and the next two bits indicate the states of the counter:

Y 00101V0100iVOniOV1001.lv 101 11-V 11 010;

Yj 00110 V 0101 1 V 0110 LOOOlV 101 0 VllOl 1;

Y, - 001 and V 01010 V О 1 1 V lOOlOV 10101 V 11001.

After entering into the register 26 of the priority code and the margin in the distributor counter, at the distributor code corresponding to the maximum priority W, a single signal appears, which opens the inhibit circuits associated with this distributor output. As a result, the MP with the priority appears connected to inputs 17, 19; 21, 23, 25 devices, but still disconnected from the common random access memory (OOP) by bus drivers 12-15. This connection takes place for a time equal to the period of the pulse generator 1, the duration of the working cycles of the recording C5, c and reading t is the total, working memory must satisfy the ratio tp j, max (, t :),

On the next generator pulse increases by. unit of its content distributor counter, again

A priority code is entered at input 27 and a single signal (pulse) appears at one of the outputs of the pulse distributor, which opens the next group of inhibit circuits and connects the next MP to the input poles of the device. So, in turn, in accordance with the priority, all MPs are connected to the OOP. The period of the cyclic change of the signals at the outputs of the distributor 3 is equal to the follow-up period. signals at the output 32 of the pulse generator, which are used to synchronize the operation of the MP and determine the duration of their machine cycles.

The occurrence of the next clock pulse at the second output of generator 1 causes the appearance at pulse 2 of the driver. The former 2 provides the fulfillment of the time conditions for the write and read cycles of the used memory.

When addressing the i-ro MP (i 1, N, where N is the number of MPs connected to the device) to the OOP, a single ib: pi appears at the i-th end of the distributor, which opens the i-th group interdiction circuits and connected to the input of the device (from i-ro MP) 1П1 to 25 addresses, bus 19 write signal iin bus 7 read signal, bus 21 read from OOP information and bus 2 write to OOP information.

The address from the i-ro MT comes through address spike 25 through the prohibition circuit 24 111 the input of the bus driver 12. At the control input, the bus driver 12 is opened with a signal from the output of the driver 2, and during the duration of this signal the address is transmitted through the bus driver 2 OOP bus (Fig. 2).

When writing data to the OOP, the recording signal goes to the i-th input 19 and through the prohibition circuit 18, opened by the signal from the 1st output of the distributor 3 pulses, to the input of the And 5 element opened by the second input by the signal from the decoder 8 address, and allows the entry information in the register 10 Records.

The information to be recorded from the output of the i-ro MP arrives at the i-th input 23 and through the scheme 22 prohibiting the register 10.

The signal from the element And 5 is also fed to the input of the trigger 11 and recording 0

five

0

five

0

five

0

five

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em with a signal at the recording input from the imager 2.

From the trigger output, a single signal is fed to the input of the And 7 element, opened at the second input by the signal from the | form of the driver 2. From the output of the H 7 element, the control single signal allows the information to be recorded to pass from the register 10 through the bus driver 14 to the information slots in OOP.

From the output of the address decoder 8, a single signal is fed to the input of the AND 4 element, opened at the second input by a signal from the driver 2, From the output of the And 4 element, the single signal is fed to the input of the bus driver 13, to the second input of which a trigger signal is output from the trigger. From the output of the bus driver 13, a single signal as a recording signal is transmitted to the write bus to match the OOP.

So, when writing to the OOP, the write signal (single), the address code to the OOP address bus and information, is transmitted. to be written to the OOP information bus. When reading the iM MP information from the OOP from the i-th sh-19 of the record, there is a zero signal (since there is no record), which is transmitted through the prohibition circuit 18 on the And 5 element, from the output of which this zero signal goes to the information input of the trigger The output of which also produces a zero signal, which is transmitted to the control driver of the bus driver 13. From its output, the zero signal as a read signal is transmitted to the control write write bus in the OOP.

The transfer of the address code to the address bus in the OOP when linking is the same as when writing information, i.e. The address code on the i-th bus 25 of the address through the i-th scheme 24 of the ban goes to the bus driver 12, the open unit signal from the driver 2. From the bus driver 12, the address is transmitted to the address bus of the OOP.

The information on the OOP bus is read to this address by input to the Register of Reading 9. Its control input receives an enable signal through the chain: i-th input 23, decoder 8 addresses, element

; And 4 (open on the second entrance of C1-1gnal from the driver 2). The signal from; the output of the element And 4 read from the UOP information is recorded in the register 9.

The Fascination signal arrives at the i-th input 21 through the circuit 20 of the prohibition of the element I 6 (the second input of which receives a single signal from the desh output || of the 8 address). From the output of the element And 6, the enabling signal permits the issuance of the read from the OOP and the number entered on the register 9 through the pin driver 15 to the i-ro bus 17 through the i-ban prohibition circuit J6,

Claims (1)

Claims of the priority memory access device, comprising a pulse generator, a single pulse shaper, a pulse distributor, an address decoder, a trigger, four AND elements, four bus shapers, a write register and a read register, with the pulse generator output connected to the input of the single pulse generator and the input of the pulse distributor and is the clock output of the processor clock device, the output of the single pulse generator is connected to the first inputs of the first and second elements And, the enable input of the first bus driver and the trigger installation input, the address decoder output is connected with the second input of the first element And and the first input of the third and fourth element And, the output of the first element And connected to the input I of the resolution of the second bus form He also entered the read register entry,: the second INPUT of the second I-junction is connected to the direct trigger output and the I-input and the .in. input of the second bus driver, the output of the second element I is connected to the enable input of the third bus driver, whose output is informational input and output of the device and connected to the information input of the read register, whose information output is connected to the same input of the fourth bus driver, the output of the third element I is connected to the information input of the trigger and input recording register of the record, the output of which is connected to the information input of the third bus driver, the output of the fourth element I is connected to the input . . | Q (5 20, 25 z q q5 35 55 The resolution house of the fourth bus driver, the outputs of the first and second bus drivers, are the address and write-out outputs of the device, respectively, about a ton of tea. that, in order to reduce hardware costs and expand its functional capabilities by quickly changing the processor access sequence to shared memory, it contains a group of address barring circuits, a group of write-recording prohibition schemes, a group of reading-signal prohibition schemes, a group of suppressing information prohibitions , a group of prohibitions of the recorded information and a priority register, with the k-th address device input (k 1, N, where 1 is the number of processors connected to the device) connected to the input of the k-th prohibition inhibitor circuit All groups of the group address banning circuits are connected to the information inputs of the address decoder and the first bus driver, the k-th input signal of the recording device is connected to the input of the k-th signal group recording ban circuit, the outputs of the prohibition signal of the group recording signal are connected with the second input of the third element AND, the k-th input signal of the device reading is connected to the input of the k-th group inhibit signal, the outputs of the inhibit signal of the group reading signal are connected to the second input of the fourth element And, the k-th information output Connected, with the output of the k-th block of the read information group, the inputs of the ban of the read information of the group are connected to the information output of the fourth bus driver, the k-th information input of the device is connected to the input of the ban of the recorded information of the group, the outputs of the ban of the recorded information the groups are connected to the information entry of the register of recording, the device’s priority input is connected to the information | 1рп-1 input of the priority register, the output of which is connected to the input of the pulse distributor, the reset of which is connected to the device's same-time input, the register entry input is connected to the output of the pulse generator, the enable input of the k-x inhibit circuits of all groups is connected to the k-th output of the pulse distributor Fig: 2