SU1383375A1 - Device for interfacing data source and data receiver - Google Patents

Abstract

The invention relates to computing and information-measuring equipment and can find application in organizing the exchange of information between devices operating at different speeds. The device transmits information from one device to another with its preliminary recording in the buffer memory. The aim of the invention is to improve the speed of the device containing a register 9, three flip-flops 7, 8 and 18, four delay elements 3-6, a reversible counter 10, a decoder 13 zero, write counters 12 and read 11, memory I, three groups of elements And 14, 15, 2, element 17 and two elements NOT 22 and 23. A group of elements OR 34, a group of elements AND 30, two elements OR-NOT 25 and 26, an element NOT 35, five elements OR 27, 31 are entered into the device. , 32, 33, 29, two elements And 24, 28, which provide increased speed by transmitting information directly from input 3 8 to the output 39 of the device without writing it to the memory .1, if the memory is not full. 1 il. s (L 00 00 con ate

Description

The invention relates to computing and can be used in computing systems for the asynchronous transfer of information from a source to a receiver of information operating at different speeds.

The aim of the invention is to improve the speed of the device.

The drawing shows the block diagram of the device.

The device contains memory 1, the third group of elements AND 2, the first through fourth delay elements 3-6, the first 7 and second 8 flip-flops, register 9, reversible counter 10, read counters 11 and writing 12, decoder 13 zero, first and the second group of elements AND 14 and 15, the first group of elements OR 16, the first element AND 17, the third trigger 18, consisting of the first 19 and second 20 elements AND-NOT, memory block 21, the first 22 and second 23 elements NOT, the second element AND 24, the first 25 and second 26 elements OR NOT, the first element OR 27, the third element AND 28, the fifth element OR 29, the fourth The second group of elements is AND 30, from the second to the fourth elements OR 31-33, the second group of elements is OR 34, the third element is NOT 35, the read inputs 36, records 37, information 38, information output 39, first control 40, address 41 and the second controlling 42 inputs.

The device works as follows. In the initial state, the counters 11 and 12, the reversible counter 10, the triggers 7 and 8 are cleared, the potential input corresponds to zero at the address input 41 of the memory unit 21, the potential of the unit is found at the output of the decoder 13, and the inputs NE OR 26 -potential zero, therefore, at its output there is a potential of a unit, which through the elements OR 27, 31 and 32 goes to the inputs of the elements NOT 22 and 23, which prohibits accessing the memory unit.

When information arrives at input 38 in the form of a parallel code, a signal arrives at input 37, which enters information from input 38 into register 9 and sets trigger 8 to one state, meaning a request to write information to memory device 21 of the device. The write request from the direct output of the trigger 8 is fed to the input of the trigger 18 and to the input of the element OR NOT 26. If there is no request for reading, a zero potential is set at the second output of the trigger 18. At the outputs of the elements OR-NE 25 and 26, there are zero potentials that allow access to the memory unit 21. At the output of the element NO 23, a write signal is set (the potential of the unit), according to which information is copied from register 9 to the memory block at the zero address. The address code that is being recorded is fed to input 41 of block 21 from counter 12 output through AND 15 and OR 16 elements. The length of the write signal at input 42 of memory block 21 is determined by delay element 6. By resetting the recording signal, the code entry in block 21 is completed, the contents of the counter 12 and the reversible counter 10 are increased by one. This completes the write request service cycle.

When a read signal is applied to the input 36, a trigger 7 is set to one state, meaning a request to read information from the device memory unit 21. In the presence of a potential of a unit at the output of the de-blocker 13 zero, at the outputs of the elements OR-NOT 25 and 26, the potentials are set to zero, which allow access to the memory. The read request, if there is no write request, goes through the element 17 to the input of the trigger 18, and its first output is set to a low potential, coming through the element OR 31 at the input of the element NOT 22. At the output of the element NOT 22, a read signal (potential of unity) is set. This delayed signal, provided by the delay element 3, is fed to the input 40 of the memory block 21, allowing reading of information and issuing a code through the AND 2 and OR 34 elements to the output 39 of the device. At the same time, the code of the address at which the reading occurs is supplied from the output of the counter 11 through the elements AND 14 and OR 16. The signal duration is read-and input 40 of the block 21 is determined by the delay element 3. By resetting the read signal, reading from block 21 is completed, the contents of counter 11 are increased, and reversible counter 10 is reduced by one. This completes the read request service cycle. When the next read signal arrives at device 36, the read request service cycle is repeated.

If all information is read from block 21, the contents of the reversible counter 10 becomes equal to zero, as a result of which the zero decoder 13 forms a potential zero, the blocking element AND 17. The read request received to the device after that is not served, but is stored in trigger 7, on the output of the OR-NOT 25 element is formed by the potential of a unit, which is supplied through the OR elements 27, 31 and 32 to the inputs of the HE elements 22 and 23, the output of these elements is set to zeros that prohibit & block 21 access. The potential of the unit from the output of the IL element AND-NOT 25 also enters the input element HE 35, the output of which sets a potential zero, which closes the element 24, thereby blocking the input of the counter 12 and the summing input of the reversing counter 10. When the input signal of the device 37 arrives, the write request information is entered register 9, and trigger 8 is raised to one. At the output of element 28, the potential of a unit is established, which opens the group of elements 30 and the information from register 9 enters through the group of elements OR 34 at the output of the device. The potential of the unit of the output element of the AND 28 element also enters through the OR elements 29 and 33 to the delay elements 6 and 3, respectively, which ensures that the read and write signals are cleared. The contents of the counters 11 and 12 of the reversible counter 10 remain unchanged.

In the case when, during the service of the write request, the first code in block 21, i.e. at the input of the decoder 13 zero there is a potential zero, a read request is received, then at the output of the element OR NOT 25 a potential of a unit is established which blocks the access to memory block 21, and through element NOT 35 closes the element 24, thereby blocking the input the counter 12 and the summing input of the reversible counter 10. At the output of the element 28, the potential of the unit is established, which opens the group of elements 30 and the information from the register 9 enters through the group of elements OR 34 at the output of the device. The contents of the counters 11 and 12, the reversible counter 10 does not change.

The blocking element And 17 is released after writing at least one code into the block 21 of the memory.

If the read signal at the device input 36 arrives during the service of the write request, and the blocking element AND 17 is removed, the read request signal is blocked until the end of the write request service, i.e. before resetting trigger 8. After resetting trigger 8, the read request service cycle begins. Similarly, if the write signal to the device input 37 arrives during the read request service, the write request service begins after the end of the read request service, i.e. after resetting the trigger 8.

In the case when there is a recorded information in the memory and at the same time recording and reading signals are received, the trigger 18 is set to one of two states. Let, for example, this be the state when the output potential of the AND-HE element 20 is set to a potential zero outputted from the output of the element OR 32 to the input of the element NOT 23. From the output of the element NOT 23, the potential of the unit is output (write request). At the end of the service cycle of the write request, trigger 8 is set to zero, thereby permitting the execution of the read request service cycle. At the end of the read request service service cycle, trigger 7 is also set to the zero state. This completes the service procedure for simultaneously entering and reading requests to the device.

Claims (1)

Invention Formula A device for coupling the source and receiver of information containing a register whose information input is an input of a device for connecting an information output of an information source, a first trigger whose installation input is an input of a device for connecting the information output sync output, a second trigger whose installation input is the device input for synchronizing the source of information and is connected to the synchronous input of the register, the output of which is connected to the information input of the memory, the address the first input of the first group of the first group and the first group of the first and second inputs of the first group are connected to the outputs of the AND elements of the first and second groups, the first inputs connected respectively to the output groups of the read counter and the write counter, the reversible counter, the output connected via a zero decoder with the first input of the first, element I, the second input and output of which are connected respectively to the direct output of the first trigger and the installation input to “1 of the third trigger, installation input to“ O, connected to the output of the second trigger, four delay elements, the outputs of which are connected respectively to the reset input of the first trigger, the first inputs of elements AND of the third group, the input resolution of the memory recording and the reset input of the second trigger, and two elements NOT, the outputs connected respectively to the inputs of the second and the third delay elements, the output of the first element is NOT connected to the counting input of the read counter, the subtracting input of the reversible counter and the second inputs of the AND elements of the first group, the output of the second element This is NOT connected to the second inputs of the AND elements of the second group, the group of memory outputs is connected to the second inputs of the AND elements of the third group, which is different (in order to increase the speed of the device, the second group of OR elements is entered into it, the fourth group of AND elements, two elements OR NOT, the third element is NOT, the second and third elements are AND and five elements OR, and the outputs of elements AND of the third and fourth groups are connected respectively to the first and second inputs of the elements OR of the second group, the outputs of which form the output of devices connection to the data input of the data receiver, summing input of down counter connected to the counting input of the counter recording and inverse output of the second element AND, the first input of the fourth delay element connected to the output, and the second input through the third element NOT with the first inputs of the first OR element and the third AND element and the output of the first OR NOT element, the first and second inputs of which are connected respectively to the output of the decoder zero and the inverse output of the first trigger, the output of the first element AND connected to the first input of the second element OR NOT, the second input of which is connected to the output of the second trigger and the second input of the third element And, and the output - to the second input of the first element OR, the output connected to the first inputs of the second and third elements OR, the outputs of which are connected respectively to the inputs of the first and second elements NOT, and the second inputs respectively to the inverse and direct outputs of the third trigger, the output of the third element AND is connected to the first inputs of the fourth and fifth elements OR whose outputs are connected to the inputs of the first and fourth delay elements, and the second inputs are respectively to the outputs of the second and third delay elements, the register output is connected to the first inputs of the elements AND the fourth group Uppa, the second inputs of which are connected to the output of the third element I.