SU1278868A1 - Interface for linking computer with peripheral unit - Google Patents

Abstract

The invention relates to computing and can be used to interface specialized external devices (VCA) with a block-multiplex channel for input-output of a computer. The aim of the invention is to improve the speed. The device contains a register, a memory block, read and write counters, a reversible counter, a block length counter, five flip-flops, six delay elements, two NOT elements, three AND elements, two OR elements, two groups of AND elements, a group of OR elements , three decoders. 3 il. with S (I'm with

Description

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00 The invention relates to computing and information measuring equipment and can be used to interface various sources and receivers of information at different speeds, in particular, specialized external devices (VCA) to study speech and diagnose complex mechanisms by their acoustic noise with a block multiplexed EU I / O channel. COMPUTER. The aim of the invention is to improve the speed of the device. Fig, 1 shows a block diagram of the device; Fig. 2 is a graph of the number of filled cells of the device's memory block as a function of time; Fig. 2, time diagrams explaining the operation of the device. The device for interfacing the computer with an external device contains a block 1. memory, register 2, first delay element 3, read counter 4, reversible counter 5, first trigger 6, third delay element 7, write counter 8, first decoder 9, groups 10 and 11 elements, a group of 12 elements OR, entry 13 entries, 14 read out the information and device information input 15, information output device 16, the second trigger 17, the first element 18, the fourth 19 and the second 20 delay elements, the third trigger 21, the elements NOT 22 and 23, exit 24 escort info The device is rotated, Fifth 25th and Fourth 26 triggers, counter 27 block lengths, second 28 and third 29 depifators, second 30 and third 31 AND elements, elements OR 32 and 33, fifth Fifth 34 and sixth 35 delay elements, input 36 signals of the end of the transmission of the array device, the second output 37 of the request for joining, the first 45

exit 38 request for coupling and exit 39 of the device overflow,

In addition, the following are indicated (FIG. 2) ;: C is the number of filled cells of the device’s storage unit; E is the capacity (number of cells) of the device memory; j M is the length of the information block (number of cells) counted from the device; T p - response time of the device receiver to the request to read a block of information from the device; TCf-time to read the block of information of the length K; T is the time of the request for reading the information block 9. 9. Triggers 6 and 17 on the read and write pulses on the inputs 14 and 13 of the device memorize. Respectively, the request for reading

one reference (or memory location) of information from the device and a request to record one reference.

To resolve the conflict when a recording device impulses are sent to the device at the same time, a priority scheme is created, formed by trigger 2.1 and NOT 22 and 23 elamants. When simultaneously receiving recording requests, t is the instant of equality of the number of filled cells of memory block 1 to the length M of the information block ; t -. the moment of the beginning of the scan of the information block from V. memory cells; t is the moment of equality of the number of memory cells read in the current block of information by the number f t is the moment of arrival of the signal of the end of the array transmission from the source device; tj - the moment of issuing the signal of the end of transmission to the device receiver. The discreteness of the function C (t) in FIG. 2 is not shown. FIG. 3 shows the time diagrams of the signals at the outputs of the corresponding elements and the input-output devices of the device, explaining its operation. The write counters 8 and 4 readings form the address of the information to be written or read from block 1, respectively. The up / down counter 5 counts the filled cells of the memory block 1 and when filling the M cells, the decoder 28 allows the installation of the trigger 25, issuing a request to read the information block from the device via the OR 33 element. The counter 27 of the length of the block of information counts the number read in. the current block of memory cells, and after reading the M cells from the output of the decoder 29, permission is given to reset trigger 25 and, accordingly, reset the request to read the information block. The OR 32 and Delay 35 elements eliminate the effects of transients in decoders 28 and 29 on the trigger 25, Trigger 26 memorizes the signal of the end of the array transmission coming from the source device, and forcibly sets the request signal to read the information block at output 38, which is reset After reading all the filled cells of the memory block by the output signal, read the priority scheme and carry them out in time. The device works as follows. In the initial state, the counters 4, 5, 8, and 27 and the triggers 6, 17, 25, and 26 are reset, and the two potentials of the trigger 21 have the same potentials (high). When a parallel code device arrives at input 15, a write impulse arrives at input 13, which enters the code from input 15 in.: Register 2 and sets trigger 17 to one state, meaning the request to write information to memory block 1. A request for writing from the trigger output 17 by a high potential arrives at the second input of the trigger 21, and if by that time there is no read request at the first input of this trigger, then its second output is set to low potential, dial, and the output element HE is service potential records This potential with the delay provided by the delay element 7 is fed to the input of the recording of memory 1, rewriting the information from register 2 to the memory at the zero address. The address code that is being written to is fed to the address input of memory 1 from the output of counter E 8 through a group of 11 elements AND open service potential recordings from the output of HE 23, and a group of 12 elements OR, Duration of the recording signal at the corresponding input of the block delay element 19, the signal from the output of which resets the trigger 17. to the zero state, thereby resetting the potential of the recording service. By resetting the recording service potential, the code entry in the memory block 1 is completed, the contents of the counter 8 and the reversible counter 5 are increased by one, and the locking potential is removed from the output of the decoder 9. This completes the write request service cycle. When the next code arrives at input 15 and the record maintenance signal as input 13, the record request service cycle is repeated. In the result, the address at the input of the memory 1 is set to the corresponding address, which in block 1 records from the register 2 the input to input 15 and the code stored in the register, and then the content of the reversing counter 5 and counter .8 records increased by one more. Similarly, further filling of the memory cells of block 1 takes place. After filling the AND cells in memory block 1 (time t ,, Fig. 2), i.e. after resetting the M-th in terms of the service potential of the recording at the output of the element HE 23, the potential output of the reverse counter 5 contents to the number M is output from the first output of the decoder 28 (the code in counter 5 tells how many memory cells of block I are filled). This potential is fed to the single-input input of the trigger 25. The installation of the trigger 25 when the resolution is different at the single input occurs on the impulse to its spawn input. Impulse sync trigger. 25 arrives every time after resetting the service potential of the write at the output of the element HE 23 or the potential of the service of reading at the output of the element HE 22 with the delay necessary to finish the transition 1x processes at the outputs of the decoders 28 and 29. This pulse is generated by the elements OR 32 and delay 35. Setting the trigger 25 means issuing a request for blocking the information block to the device output 37, and to the installation input of the counter 27 block length means allowing this counter to work, With the delay Tp (FIG. 2), equal to the kana response time and input-output to the request for reading a block of information, the device 14 starts to get to the device input 14. (time t,, Fig. 2) the scans are read at a frequency several times greater than the frequency of the recording pulses at input 13 (time interval). Fig. 2). When a read pulse is sent to input 14, trigger 6 is set to one, meaning a request to read the ir; formations from memory block I. This request through the element 18, the potential open from the output of the decoder 9, arrives at the first input of trigger 2, and if by this time there is no write request at the second input of this trigger, then a low potential is established at its first output, and .22 is the service potential of SSTNT. This potential is fed to the read input of memory 1, allowing reading and issuing information from it at the output 16 of the device.

The code of the first address (zero), which is read, is fed from the output of counter 4 through a group of 10 AND elements, opened by the read service service potential from the output of the HE 22 element, and a group of 12 OR elements. With the delay necessary to establish information on the output 16 of the device and provided by element 3, the output 24 of the device produces a signal with the information, the duration of which is determined by the delay element 20.

The signal from the output of element 20 resets the trigger 6 to the zero state, thereby resetting the potential of the read service. By resetting this potential, the reading from memory block 1 is completed, the contents of counters 4 and 27 are increased, and the reversible counter 5 is reduced by one. This completes the count query query service cycle.

When the next read pulse arrives at input 14 of the device, the read request service cycle is repeated. In this case, the code of the second address is set at the address input of the memory block 1. The information is calculated from this address and is outputted to output 16, then one more unit is subtracted from the contents of reversing counter 5, and one is added to counters 4 and 27.

In the case of a partial overlap in time of the write and read pulses at the inputs 13 and 14 of the device, the priority circuit consisting of the trigger 21 and the elements NOT 22 and 23 starts the service cycle of the request that came first. When simultaneously receiving pulses at the indicated inputs of the device, the sequence of service cycles is determined by e- with the internal parameters of the trigger 21,

After reading the M memory cells (time t, Fig. 2), the corresponding signal from the output of the decoder 29 is transferred to the zero input of the trigger 25. The reset of the trigger 25 occurs by a pulse from the output of the delay element 35 and causes the counter 27 of the block length to reset on the installation output and

stopping the arrival of read pulses at input 14 of the device.

Reading the block of information occurs. For the time interval T

(Fig. 2), and the duration of the request signal for reading a block of information at the output 37 of the device is T ,,. ,

In the process of reading the block of information (formations from the device and after the end of the reading of the block of information, the process of writing information to the device continues. When the next M memory cells are filled again from

A request is made to the device to read the information block and to detect the blocking of this block. The described process continues until the pulse of the transmission end arrives at the input 36 of the device.

array of data from the VCA. Counters 4 and 8 recalculate the pulses arriving at their counting inputs modulo E, where E is the capacity of the device’s memory, i.e. for example, after recording at address E - 1, the next entry of 1 memory occurs at the zero address.

Having completed the transfer of an array of information, the VCA sends, for example, at time t (Fig. 2) to the input 3S of the device a pulse of the end of the transmission of the array. This pulse sets the trigger 26, the signal from the output of which is output through the element OR 33 to the output

37 of the device as a request for matching a block of information.

When the trigger 26 is set, information is read from the device until the content of the reversing counter 5 is zero, i.e. until all the information from the device memory 1 is read. After zeroing the counter 5 (time t., Fig. 2), the signal from the output of the decoder 9 allows the output of the array transfer signal to the channel through the element 30 and the device output 38. Simultaneously signal

the end of the transmission of the output element And 30 enters through delay delay 34 to the zero input of the trigger 26 with a delay determined by the element 34, and resets the trigger 26. The duration

The signal at the output 38 of the device is also determined by the delay time of the element 34. Upon the pulse of the end of the transmission at the output 38 of the device, the arrival of input pulses at input I4 is stopped, and the device is terminated.

After filling all E cells of block 1, the potential opening element AND 31 is established at the second output of decoder 28. If after this the reading of information from the device does not start waking the next occurrence of the write pulse to the device input 13, then upon arrival of this write pulse the potential of the write service from the output of the element HE 23 through the element I 31 is output to the output 39 of the device as an overflow signal of the memory block 1.

Elements 3, 7, 19, 20, and 34 of the delay delay only the positive differential of the input signal, and element 35 delay only the positive differential of the inverted input signal.

To use the device when entering information from the VCA into the computer, information from the VCA is recorded into the device through input 15, and from there it is output to the computer channel from output 16. At the first output of the decoder 28, the resolution potential is set when the content of the counter 5 (the number of filled cells memory) becomes equal to or greater than the length M of the information block. At the second output of the decoder 28, the resolving potential is established when the contents of the counter 5 becomes equal to E, i.e. when all memory cells are full.

. To use the device when outputting information from a computer to the VCA, information from the computer is recorded into the device via input 15, and output to the VCA from output 16. In addition, the first output signal of the decoder 28 must have a enable signal when the contents of counter 5 are equal to or less than ( CM). The signal at the output 37 of the device in this case means a request to write to the device a block of information from a computer. The signal of the end of the transmission of the array from the channel is fed to the input 36 of the device, and to the VCA is output via output 38 as soon as all the information from the memory block is output to the VCA. The trigger 25 may remain in the set state, which does not affect the completion of the exchange. To generate an overflow signal (more precisely, no information in the memory block)

The resolution signal at the second output of the decoder 28 must be set with the contents of counter 5 equal to zero, and the first input of the AND 31 element must be disconnected from the output of the HE element 23 and connected to the output of the trigger 6.

Claims (1)

Q claims A device for interfacing a calculating machine with an external device, comprising a register, a memory block, a reversible counter, a write counter, a read counter, a first decoder, three triggers, four electrons, a delay element, two elements NOT, two groups of And elements, a group "OR, the first element is AND, and the information input of the register is the input of the device for connection to the information output of the external device, the single input of the first trigger is the input of the device for connection to the output of the computation tion machine, a single input of the second flip-flop is coupled to register write input and is an input device for connection to an external input recording device, an output of first DELAY 1 and connected to the input of the second delay element and the output device is for connection to the strobe input 5, the information output of the memory unit is the input of the device for connection to the information input of the computational machine, and the output of the second delay element is connected to the zero input of the first trigger, the output of which is connected to the first input of the first element AND whose output is connected to first setup input 5 of the third trigger, the first output of which is connected to the input of the first element NOT, the output of which is connected to the input of the first delay element, to the control input of the subtraction of the reversible counter, to the first inputs of the AND elements of the first group, to the read input of the memory unit and to the counting input of the counter readout, a group of outputs is connected to the second inputs of the elements AND of the first group, the group of outputs of which is connected to the first inputs of the elements OR of the group, the output group of which is connected to the group of address inputs a memory unit whose recording input is connected to the code of the third delay element and to the input of the fourth N delay element, the output of which is connected to the zero input of the second Trigger, the output of which is connected to the second installation input of the third trigger, the second output of which is connected to the input of the second element NOT, the output of which is connected to the input of the third delay element, to the control input of the addition of a reversible counter, to the first inputs of the AND elements of the second group and to the counting input of the record counter, the group of outputs of which is connected The output of the reversible counter is connected to the input of the first deprafrator, the output of which is connected to the second input of the first element I, the information output of the register is connected to the information input of the memory block, characterized in that, in order to increase speed, a block length counter, two decoders, two triggers, two delay elements, two AND elements, two OR elements, and a single input of the fourth the trigger is the input of the device connecting to the output signal of the end of the array transfer of the external device, the output of the second element I is connected to the input of the fifth delay element and is the output of the device for connecting to the first input of the request for connecting the computer, the output of the first element OR is the output of the device connect to the second the input of the read request of the computer, the output of the third element I is the output of the device for connecting to the input of the request for interrupting the computer, the output of the fifth delay element is connected to the zero input of the fourth trigger, the output of which is connected to the first input of the first OR element and to the first input of the second element And, the second input of which is connected to the output of the first decoder, the input of which is connected to the input of the second decoder, the first output of which is connected to the unit the trigger input, the output of which is connected to the second input of the first OR element and the zero input of the block length counter, the output of which is connected to the input of the third decoder, the output of which is connected to the zero input of the fifth trigger, the synchronous input of which is connected to the output of the sixth delay element, the input of which is connected to the output of the second OR element, the first input of which is connected to the output of the second element NOT and to the first input of the third element AND, the second input of which is connected to the second input of the second decoder, the second century x one of the second element OR is connected to the counting input of the block length counter and with the output of the first element NOT, 2it sixteen