SU1437865A1 - Device for monitoring digital units - Google Patents

Abstract

The invention relates to computing and can be used to control digital nodes and information processing devices during their manufacture and operation. The purpose of the invention is to expand the functionality of the device by providing the possibility of monitoring the nodes containing software and storage devices. The device contains registers 1-9, reg.- registers 10-12 of shift, switches 13-18, node 19 of elements AND, counter 20, element AND 21, element NOT 22, elements OR 23-26, block 27 of synchronization, block 28 of processing information, interface unit 29, test action generation unit 30, clock inputs 31, 32. The device provides the ability to test the combination; circuits, storage and program nodes, in addition, provide the possibility of estimating the time of forming response responses and the time you execute programs. Additional functions are provided with additional registers, shift registers, a counter, other blocks and interconnections between them. 3 il. yu (L

Description

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The invention relates to computing and can be used to control digital nodes and information processing devices during their manufacture and operation.

The aim of the invention is to expand the functionality of the device by providing the ability to control the nodes containing software and storage devices.

1 shows a diagram of a device for monitoring digital nodes; figure 2 - diagram of the synchronization unit; on fig.Z - algorithm of the information processing unit.

The device (Fig.) Contains the registers I - 9, the registers 10-12 shift, switches node J9 elements

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And, the counter 20, the element And 21, the element NOT 22, the elements OR 23-26, the block 27 synchronous probes, the block 28 of information processing, the block 29 of the conjugation, the block - 30 forming test influences, clock inputs 31 and 32. Controlling digital the node is labeled Lozisch-i-s. 33. -.

The synchronization unit (Fig, 2) contains a group of elements AND 34 and the element OR 35.

The device for controlling digital wells works as follows.

The interaction of the information processing unit 28 through the interface unit 29 with the test formation unit 30: the actions consist in that the unit 28 writes information to registers 1, 3 9 in accordance with the program or reads information from register 2 and counter 20, and in Gyms 1,4 and 5 are set to signal the effects on the control object, register 3 is recorded with the signals of the level 45 Hjw switch 14, register 2 records the response from the control object, and registers 6-9 from the block. 28, information defining the mode of operation of the device is recorded. The information in the counter 20 with a known period of the reference frequency input to the input 31, allows you to determine the length of time from the launch moment

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Suppose a node is to be monitored that requires a sequence of impact signals: submit the address of the cell being checked; reset address of checked cell; submit data for recording; give command Record; reset the Write command; reset dylnye; submit the address of the checked cell; give the command Read.

For definiteness, it is also admissible that in a write cycle the duration of an address is 2, the data enters the object under control C G after resetting the address and the duration of the data C G, the Record command comes through G after the data is received, and its duration is t. The delivery of the address in the read cycle can in principle be performed at any time, but the time relationships of the signals in the read cycle should also have certain values, the duration of the 2T address, the Read command comes 6T after the address is reset, and its duration is t. During the reads, the device should receive a response from the control object.

Before the start of control, input 32 is supplied with a reference frequency, the value of which is set in such a way that the time intervals between the signals and the duration of the signals are multiples of its period. In this case, it is most convenient that the period of the reference frequency bi1 is equal to T.

The information processing unit 28, successively referring to the registers 5 4, -1,9,8 and 7, writes the following information to the register until the moment of reading: in register 5, the value from its outputs or the moment the counter stops.

The set of registers of block 30 and their functionality allows

address of the checked memory cell (multi-position signal), to register 4, the value of the data to be written to the checked cell (multi-position

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nporpaMMio set one or another mode of operation of the device, so that it can form various complex exposure signals.

Consider the operation of the device when monitoring the most frequently used nodes: monitoring a node with a memory block, monitoring combinational circuits, monitoring the response time of a combinational circuit, and monitoring the program execution time of a program node.

Control node with memory block.

Suppose a node is to be monitored that requires a sequence of impact signals: submit the address of the cell being checked; reset address of checked cell; submit data for recording; give command Record; reset the Write command; reset dylnye; submit the address of the checked cell; give the command Read.

For definiteness, we also assume that in a write cycle, the duration of an address impact is 2, data enters the control object 3 G after resetting the address, and the duration of the C data, the Record command comes through G after the data arrives, and its duration is t. The delivery of the address in the read cycle can in principle be performed at any time, but the time relationships of the signals in the read cycle should also have certain values, the duration of the 2T address, the Read command comes 6T after the address is reset, and its duration is t. During the reads, the device should receive a response from the control object.

Before the start of control, input 32 is supplied with a reference frequency, the value of which is set in such a way that the time intervals between the signals and the duration of the signals are multiples of its period. In this case, it is most convenient that the period of the reference frequency bi1 is equal to T.

The information processing unit 28, successively referring to registers 5, 4, -1,9,8 and 7, writes into them the following address of the checked memory cell (multi-position signal), into register 4 it means the data to be written into the checked cell (multi-position

signal), to register 1 - logical 1 to the bit corresponding to the input of the Record command in the control object, while O.

The information recorded in registers 9.8 and 7 determines the durations of the acting signals and the intervals between them, in this case the information recorded in the specified registers provides the durations specified above.

If we rewrite the contents of registers 9,8 and 7 into shift registers 12,11 and 10 and apply a pulse sequence to their shift inputs, then the occurrence moments 1 at the outputs of shift registers are reset by the bit in which 1 was written originally, the duration 1 at the output depends on the number of recorded increments of d 1, and the intervals between pulses are determined by the relative position 1 in registers 12.11 and 10, respectively,

In the process of recording information in the registers 5, 4, 1, 9 and 8, no signals arrive at the inputs of the control object, since the switches 18, 17 and 13 are closed through the gate inputs. At the moment of recording information in register 7, elements AND of node 19 are opened and the contents of registers 9.8 and 7 are rewritten into registers 12.11 and 10 of shift, respectively. The information recorded in registers 12.11 and 10 begins to advance towards the higher order. /

To ensure a reading cycle, information processing unit 28 addresses registers 3,1,4,8 and 7 and writes the following information in them: register 3 records I in those bits that provide a preliminary connection of register 2 inputs to the corresponding object outputs control, in register 1 logical 1 is written to the bit that corresponds to the input of the Read command in the control object, in register 4 in all bits are written O, in register 8 in all bits are written O, in registers 5 and 9 is saved former and information

Block 28 reads information from register 2, for which it sets at the inputs of block 29 the address of register 2, which is decrypted by block 29 and in the form of a sampling signal. Inversion 1 is fed to the input of block 27. The read synchronization signal from block 28 Input is converted by block 29 into the signal Input WGD which is also fed to the input of block 27. From the signals of Appeal 1 and the Input of the FrG, the block 27 forms a switch control signal

15, which translates the contents of register 2 (response). In block 28 of information processing. In information processing block 28, the response response is compared with the reference one and the result of the comparison in the form of alphanumeric text is displayed on the display of the information processing unit.

Control of combination schemes. Before the start of control, all registers are reset (write O to all registers of their block 28). Then, in register 3, 1 is written into those bits that correspond to the outputs of the control object. The next step in the register .1 is the test signal (write signal). Then, in CTapmie, bits of register 7 are recorded 1, the number of which is determined by the time of exposure of the test signal, V

The recording of information in register 7 is recorded in register 10 and then the shift of the contents of register III begins (in registers 15 and 12

O), Logic 1s from the output of register 10 are shifted by switches 13 and 14, and information from register 1 is received at the inputs of the control object. Simultaneously, from the outputs of the monitoring object, the response through the switch 14 enters the inputs of register 2 and is wired into it. Then the response from the regaster 2 is entered into block 28 and analyzed, and the result of the analysis is displayed.

Control of response time by combinational circuit.

This mode is similar to the previous one.

At the input 32, a reference frequency is manually set, the period of which is less than the expected response time. Then, 1 is written into the higher bits of register 7. If the response does not correspond to the reference response, then an increase in the number 1 in register 7 is performed until the response responds to the reference or time

the formation of the response will not exceed the maximum allowed.

Control of the program execution time by the program node.

In this mode, fairly large time intervals are measured. The unit of time is the period of the reference frequency set manually at input 31. Then the control program is started, according to which register 1 is written 1 to those bits that correspond to the control objects. The next step 1 is written to the register bit 6, which through element 23 enters the gate input of the switch 14 and which connects the object outputs to all controls. A control signal is applied to registers 1,4 and 5 (or one of them, depending on the signal structure) and a signal (or an array of signals) is applied to the control object, which triggers the programs of the control object. Next step in time p, c register b vrdits 1, zazuskagoscha counter 20, which begins to count the number of frequency periods at input 3i, then block 28 alternately polls register 2 and counter 20. When register 2 comes from the control object responds reaction (readiness signal for the result of the executed program), block 28 takes the readings of counter 20, compares them with the permissible program execution time by the control object, and displays the result of the comparison,

As a block 28, a set of microcomputers, Electronics 60 M (2.791.004-ОЗГО) display 15-ИЭ 00-33 (ШЦМ 3.778.012ТО) and photo-reader FS - 150I are used.

Claims (1)

Invention Formula A device for controlling digital nodes, comprising a synchronization unit and a test action generating unit, comprising first and second registers, first and second switches, the first outputs of which are connected to the information inputs of the first switch, all of which are combined with the information inputs of the second switch the device outputs for under five 0 0 the keys to the control object's inputs-outputs, the outputs of the second switch are connected to the input of the second register, the input of the first register is connected to the first output of the synchronization unit, characterized in that, in order to expand the functionality of the device by providing control over the nodes containing software and storage devices in non-. first, an information processing unit, a conjugation unit, and the third to ninth registers, three shift registers, the third to sixth switches, a counter, an AND element, an NOT element, four OR elements, and a node of AND elements the groups of information inputs of the first and third, through the ninth registers and the group of information outputs of the third and fourth switches are combined and 5 are connected to the first group of information-OHiibix inputs-outputs of the counterpart block 1, the group of synchronizing inputs Dov of which are connected respectively to the syncro group} Shziruyu dikh inputs-outputs of the synchronization unit, the second to the seventh outputs of which are connected to the inputs of the input from the third. In the nine registers, respectively, the entry entry of the seventh register combined and connected to the eighth output of the synchronization unit, the ninth and tenth outputs of which are connected to the control inputs of the third and fourth switches, respectively, the output groups of the seventh, eighth and ninth registers are connected Respectively with the first, second and third groups of inputs of the node elements And, the first, second and third groups of outputs of which are connected to groups of parallel inputs of the first, second and third shift registers, respectively, the shift inputs of which are combined and connected to the output of the element And, the first and second inputs which is connected respectively with the output of the element NOT and the first clock input of the device, the second clock input of the device is connected to the clock input of the counter, the exhaust group of which is connected to the information group in odov fourth switch perzy, second, third, fourth, and five 0 five 0 five nHTbrti the bit outputs of the sixth register are connected to the first inputs of the first, second, third OR elements and the start and zero inputs of the counter, the first input of the fourth element OR is connected to the second input of the third OR element and the high bit output of the first shift register, the second inputs of the first , the second and fourth elements OR are connected to the high-order outputs of the second and third shift registers and the seventh register, respectively; the outputs of the first, second, third and fourth elements OR are connected to the strobe the inputs of the second, sixth, second Q 15 378658 first and first switches, respectively, the outputs of the fourth and fifth registers are connected to the information inputs of the fifth and fifth switches, respectively, whose outputs are a group of device outputs for connecting to the control object's input-output group; the outputs of the second and third registers are connected to information outputs the third and directed to these inputs of the second switch, respectively, the group of inputs and outputs of the information processing unit is connected to the second group of information inputs and outputs of the unit with p voltage.