SU1180876A1 - Information output device - Google Patents

Abstract

A DEVICE FOR OUTPUT INFORMATION, containing the first and second counters, an exchange unit, a memory unit, a display unit and a control unit, the first output of which is connected to the input of the first counter, the second output - to the input of the reading of the memory unit, the third output - to the input of the display unit The first input-output is with the control input-output of the exchange unit, the first information input-output of which is the information BXQ-output device of the device, characterized in that, in order to increase the capacity of the device, the first register is entered into it, the first group of elements is And, the group of elements of IRC, the second and third group of elements is And, the first trigger, block of registers, the first element OR, the fourth group of elements And, pulse shaper, the second trigger, the second element OR and the first inverter, output Koi / oporo is connected to input set to 1 of the second trigger, the input is connected to the output of the second element OR, whose input is connected to the fourth output of the control unit, five and sixth outputs of which are connected to the inputs of the installation to 1 and O of the first trigger, the seventh output is connected to the first input one pulse generator, the eighth output is connected to the installation input in O of the second trigger, the zero output of which is connected to the second input of the pulse generator, the single output of the first trigger is connected to the first inputs of the second group, the second inputs of which are connected to the outputs of the first counter, and the outputs are connected to the first inputs of elements OR groups, the second inputs of which are connected to the outputs of elements AND of the third group, and the output is connected to (L one inputs of elements AND of the first group, the other inputs of which are connected to the output m of the first OR element, and the outputs - with the inputs of the first register, the outputs of which are connected to the address inputs of the memory block, the input-output of the kortora which is connected to the first input-output of the block of registers, and the input of the recording is connected to the first output of the pulse shaper and to the first input of the first of the scientific research institute, the second input of which is connected to the second output of the control unit, the second input-output of which is connected to the second input-output of the register block, the first information input of which is connected to the first output of the exchange unit, the second information output ny zhod connected to the second output of the impulsrv, second information input-output of which is connected to second data input-output of the exchange unit, the third output is connected to the counting input (J4 second sche-rchika fourth output - to one inputs of AND gates

Description

the fourth group, the other inputs of which are connected to the first one; the house of the third group of elements I, the second exchange, is connected to the second output; the outputs are connected to the inputs, the parallel input of which is connected to the zero input of the second meter, the output of the first trigger.

1180876

The invention relates to computing technology and can be used to output information, coming from a digital computer. The goal of the ISP is to improve the ability of the device to read the device a i. In FIG. 1, a diagram of the proposed device is given; Fig. 2 is a block diagram of the control unit: gland J in Fig. 3 is a block diagram of the exchange unit; Figure 4 is a block diagram of a reg,;; FIG. 3 is a diagram of shaping; iK pulses; figure 6 - scheme V.i.5ra word processing; in Fig.7, the structure of processed words. The device (Fig. 1) contains the block i y) engraving, 1b, exchange unit 2, block 3: .1 mi, first counter 4, second), OjtoK 6 display, perliii register 7, first-group element Icr .i 1 8 , the first group of elements is linif 9, the second is 10 and the third 11 groups of cops And, the first trigger 12, block 1; meters, the first element OR 14 ,, ,,. ; ..; - |. | a group of elements And 15, fo1 - ;; p11} 5th impulse 16, second epemiitis OR 17, first inverter 18, second trigger 19. G-lok 1 control (Fig. 2) contains trigger 23 Tjjc rr-uf trigger 20, first ele; 211, the third counter 22, the first driver 23, the second group of elements) in OR 24, the word processing unit 25, the second register 26, the first group of inverters 27, the third group of elements of MIT 28, the second inverter 29, the third element OR 30 and a pulse generator 31. The exchange unit 2 (FIG. 3) contains the first group of amplifiers 32, the fourth element OR 33, the third inverter, the third register 35, the second group of amplifiers 36 and the amplifier 37. The block 13 of registers (figure 4) contains the fourth register 38, the second a group of inverters 39, the fourth group of ELOMEPT OR 40, the fourth 41, the fifth 42 and the sixth 43 groups of elements AND, the fifth register 44. The pulse shaper 16 (figure 5) contains the seventh group of elements AND 45, the second decoder 46, the fifth the element OR 47, the third inverter 48, the fourth trigger 49, the second element AND 50, the fifth trigger 51, the third element And 52, the fourth counter 53, the sixth trigger 54 and the fourth element And 55. The word processing node 25 (FIG. 6) contains the eighth 56, the ninth 57, the tenth 58, the eleventh 59 groups of elements And, the seventh trigger 60, the fifth element And 61, the sixth element And 62, the fifth counter 63, the seventh element And 64, the fourth inverter 65, the sixth element OR 66 and the fifth inverter 67. From the first output of the control unit 1 to the input of the first counter 4, the signals of its installation into O and a change per unit state for the counting input, for example, of that digit; From the second output, a signal is input to the first input of the memory block 3 to activate the read mode and to the second input of the OR element 14 for writing, to the register 7, the codes of the characters position, the codes of the characters themselves and the control signals are entered from the third output into the block 6 signals to turn on, for example, a character generator; control signals are received from the fourth viGochod to activate trigger 19; from the fifth output, the signals continue to turn on trigger 12; from the sixth output, the signal sets in O the trigger 12, from the seventh output to the second input of the imager, pulse 16 receives a pulse frequency; from the eighth exit, set to On flip-flop 19; via communication, input-output with block 13 of registers; input signals t into it; these provide the recording of information read from memory block 3. to register 38 and register 44, and receive code information from block 13 of registers to node 25. Exchange block 2 via communication, the input-output with a digital computer produces control signals at the end of exchange cycles, the frequency and reception of signals for the start of exchange, the start of exchange cycles and code signals; on communication, the input / output of the exchange unit 2 with the driver of 16 pulses, the signals for the beginning of the exchange, the beginning of the exchange cycles, the setting to O are inputted into the latter, and the signal for the end of the exchange cycles is received from it, the second output of the exchange unit 2 is entered with code information containing the starting address of block 3 of the memory of the current exchange, for the information input of the fourth group of elements I 15; From the first exit into block 13 of registers, code information is entered. On the first input of block 3 of the memory from the output of block 1 of control, the readout signal is input, on the second input - the code of the address of the cell from the output of register 7; the third input is a signal Recording from the first output of the driver 16 pulses. The first input of the first group of elements And 8 is entered from the output of the first group of elements SH 9, the address code information, and to the second input a control signal from the output of the first element SH 14, the output of the address code of the cell is fed to the input of the address register 7. Trigger 12 s the zero arm inputs a signal to the control input of the third group of elements I 11, and from a single shoulder to the control input of the second group of elements 10. The information inputs of the second group of elements 10 and the third group of elements 11 enter the corresponding shoulders of the first 4 and second 5 counters, and the code information from the outputs of the first 10 and second 11 groups of elements AND are inputted to the corresponding inputs of the first group of elements 9). To the second input of block 13 of registers, a signal is written to write to register 38 from register 35. First and second the inputs of the first element OR 14 are input signals Write and Read, respectively, from the first output of the driver 16 pulses and from the second output of the control unit 1. At the first input of the imaging unit 16 pulses, the signal is inputted from the zero arm of the flip-flop 19, from the third OUTPUT to the second input of the second counter 5, the installation signals to O and the signals to the counting input are input, and from the fourth output to the first input of the fourth group of elements 15 to interrogate the code of the starting address supplied from the second output of the exchange unit to the information input of this group, and enter this code to the second input of the second counter 5. The device operates as follows. The information displayed in block 6, for example, on a CRT screen, is recorded in memory block 3, and the control block 1 in the process of displaying performs sequential (one after another) reading of words from memory block 3 using the first counter 4, which through the second the group of 10 and 10 lemmas, the first group of elements OR 9 and the first group of elements AND 8 are connected via register 7 to block 3 of memory at certain points in time. In the display process, the first counter 4 takes values from the first cell address code in memory block 3, where the first word of the array is written and from which the display cycle begins to the address code of the last cell into which the last word from the array of words is written. intended for display. In order to extract the chunks from the word memory block 3 and their subsequent processing, the control block 1 generates time-separated control signals, for example, read word read signal. Connecting the second counter of address 4 to memory block 3, counting down the time for testing the read cycle in memory block 3, generating signals for rewriting the cell contents to register 38 of register block 13, then to register 44 for connecting to word processing node 25 where the type of the word read (coordinate, character, end of the array) recorded in the attribute part of the word (for example, in the first bits) is determined and, depending on this, its information part is processed and entered into block 6. ndVuie from the memory block, 3 memory The last word of the array and its processing are set to the original (O) first counter 4 and the imaging cycle is repeated. To ensure a stable image, for example, on a CRT screen, it is necessary to regenerate the information recorded in memory block 3 with a frequency of about 50 Hz and not to interrupt the display cycle for the duration of the exchange. Information is exchanged with a digital computer using an exchange unit 2, in which, through the second group of amplifiers 36, code information is exchanged between the digital computer and the register 35. Through the first group of amplifiers 32, control signals are exchanged between the digital computer and the driver 16.

Information from register 35 is entered into memory block J using a pulse generator 16 and a second counter 5, designed to store the current address of the cell into which information is recorded. During the exchange, the output of the second counter 5 is connected through third at certain points in time. a group of elements And 11, the first group of elements OR 9, the first group of elements And 8 and a register 7 to block 3 of memory.

The information recorded in register 35 is rewritten into register 38 and then entered into memory block 3 to write to a cell, p1 whose address is at that moment recorded in the second address counter 5.

At the time of the exchange cycles, the register 44 contains a word (read before the start of this exchange cycle) that processes the control unit 1 to create an image in block 6. To ensure continuous display of information during the exchange cycles, the memory block 3 is accessed reading of the word to be displayed is performed without delay, with priority before accessing memory block 3 to record the words received in the process of receiving information from the DVR.

Thus, the device provides, simultaneously with the performance of the digital exchange, the display of information in block 6, and the display mode, having a transform

access to memory block 3. On the read rem from block 3, the memory of the slice intended for displaying and writing it to the register 44 generates a signal from the output of the control block 1, which turns on the trigger 12, resulting in the code of the first counter 4 through the second group of elements OR 9 the input of the first group of elements is AND 8, to the control input of which through the first element OR 14 receives a signal from the second output of the control unit 1. As a result, the register 7 records the address of the cell from which information is read for display.

Before reading the word for display, the fourth output of control unit 1 receives a signal to activate trigger 19, which from this point on prohibits an exchange cycle, i.e. if, after switching on trigger 19, a signal arrives (start of word, beginning of exchange) the beginning of the exchange cycle, it is remembered on trigger 49, not the start of the exchange cycle. After the completion of the compilation of a new word for displaying (writing it to register 44), the sixth and eighth outputs of control unit 1 receive signals to set O, respectively, trigger 12 (to connect to register 7 of second counter 5) and trigger 19 (to allow exchanging) . Before the next call to the memory block 3 to read the next word to be displayed, the signal from the fourth output of the control unit 1 again triggers flip-flop f19 for the time required for the complete (one-word) exchange cycle. If the exchange cycle begins before this point, then by the beginning of the access to the side 3 memory after the word to be displayed it is already finished. If the signal for the start of the next exchange cycle comes after blocking the driver of the 16 pulses, then it is remembered and the activation of the exchange cycle occurs immediately after installation in the initial trigger 19.

Before starting work from the digital computer, through the first group of amplifiers 32, the control unit 1 and the shaper 16 pulses enter the installation signals into O, and then enter the signal to activate the trigger 20 through the first control unit. As a result, through the first element 21, the input of the counter 22 and The first decoder 23 begins to receive the frequency. As the counter 22 operates, the signals separated in time appear successively at the outputs of the decoder 23. Each position of the counter 22 corresponds to only one output of the decoder 23, i.e. choosing, for example, as a counter 22, a seven-digit counter and connecting it to the corresponding decoder 23, up to 128 control signals are received at the output of the latter, which are conventionally divided into several groups (programs), the signal, each of which is designed to tasks. For example, the information display mode consists of several tasks — first read a word from memory block 3, for which you need to set the code on register 7 and input a read signal from memory control 1, then read the register 38 read the word, rewrite it to register 44 and analyze the type of this word in the word processing node 25. In the device, for example, three types (types) of words are used - coordinate, signed, end of the array, which differ from each other in both informational and indicative part, which contains the sign of the word type (for this purpose, for example, the first three bits are allotted) . Each of these words requires its own control signals to process. After determining the number of these signals (taking into account the timing diagram), they are conventionally formed into groups of additional categories from the output of the first decoder 23, i.e. form, for example, a group of (first) signals, starting with the first one, which enable trigger 12, enable trigger 19, write the address code to register 7, turn on memory 3 in read mode, write the read word from memory 3 in register 38, rewriting a word into registd5 44, and polling the type of word in node 25 of word processing. The next group of signals, ng arimer, for processing zero (information) words begins immediately with the last signal of the first group and consists of, for example, eight clock cycles. Null words are in block 3 of the memory immediately after powering up the device, when the digital computer does not information was recorded, and the display mode was turned on. The last signal of the zero program writes the next state through the second group of elements OR 24 to the first counter 4 and sets the counter 22 into О to activate the reading mode of the next word (the first group of signals). The next group of signals, for example, for processing a coordinate word, begins immediately after the last signal of the previous group of signals (zero). The signals of this group record the code of the coordinates (position) of characters contained in the word, register 26, count the time required to output a CRT beam to the corresponding point on the screen, record the next state on the first counter 4 and, with the last signal, set the counter to zero 22 The next group of signals, for example, for processing a sign word, begins with the signal following the order of the last signal of the previous program and provides input of character codes sequentially one after another into block 6, inputting start signals cogenerator, state change coordinate register (on X axis) space to the mark on the line, after processing, recording next state for the first counter 4 after the sign processing and installation in the ON counter 22 to read the next word of the memory block 3. The next group of signals, for example, to process the last word of the array (the end of the array begins with the signal following the last in the previous group. The signals of this group ensure that the first counter 4 is set to O and the counter 22 is set to O, i.e. the end of the cycle and Preparing for a new display cycle. Each time after reading a new word. The last signal from the first group of signals from the output of the expander 23 analyzes the attribute part (type) of the word being read - polling the eighth group of elements And 56. For example, the code corresponding to the first signal from the corresponding group (depending on the type of word) of the signals from the decoder 23 is set to counter 22. The transition to the first signals of each group always occurs from one counter state 22, and m-ieHHO at generating the last signal of the first group. Only when switching to the processing of the zero word, the counter 22 continues counting the program, since in this case the output of the eighth group of elements And 5 does not appear in the code line ne ehoda counter 22. For organization-compensation code transition use tiruyuschie codes. Counter 22 in this case provides the possibility of parallel recording by counting input of each bit individually. Then, with a known source code (the last signal of the first group) and known code values for the first signals of each group, a correction code for each group is determined. For example, if the last signal of the first group is generated with the code 0001001 counter 22 and the first signal of the third group with the code 01010010, then the transition code in this case will be 01011011 (the transition code is the value that is added to the original in a definite way) . Thus, after zeroing and activating the trigger 20, through the first element 21 and 21, the frequency arrives at the input of the counter 22 and the decoder .23, and control signals appear at the output of the decoder 23. As discussed above, the first signals belong to the first group and provide the reading of a word from memory block 3. They come from the output of the decoder 23 through the fifth output of the control unit 1 to the installation in 1 of the trigger 12 for connecting the counter 4 through the second group of elements AND 10 and the first group of elements OR 9 to the first group of elements And 8, and through the second output of the control unit 1 to a memory unit 3 for switching on the mode (Read) and simultaneously via the first element OR 14 to the second control input of the first group of elements AND 8 for writing the cell code to the register 7. The following signals from the decoder 23. are received through two-way communication in block 13 registers for rewrite si read the word from the numeric register of memory 13 through the sixth group of elements And 42, the fourth group of elements. OR 40 and the second group of inverters 39 to register 38 and then through the sixth group of elements AND 43 to register 44, from the output of which information is entered into the word processing unit 25 of the control unit 1. The following signals from the output of the decoder 23 are received through the sixth and eighth outputs of the control unit 1 to be set to O, respectively, trigger 12 and trigger 19. The next signal from the output of the decoder 23 interrogates the eighth group of elements And 56, from the output of which it goes to the line of the corresponding (type read the word) transition code and sets on the counter 22, through the third group of elements 28 and the first group of inverters 27, the code corresponding to the output of the decoder 23 to the first signal of the selected group. When processing the coordinate word, the first signal of this group from the decoder 23 enters the word processing unit 25 for polling the tenth 58 and eleventh 59 groups of elements AND, whose second inputs receive signals from the unit triggers of register 44, containing the coordinate codes X and Y, and these codes will be written to register 26. As a result, this code is entered through the third output of control unit 1 into block 6 and, for example, the process of inserting a CRT beam into a given point of the working floor of the screen begins. At this time, the counter 22 counts the time required for the output beam, after which the last signal of the group passes through the second group of elements OR 24 to set the next state on the counter 4, as well as through the third element OR 30, the second inverter 29 and sets the counter to O 22, thereby enabling the next word reading program (the first group of signals). When processing the sign word with the decoder 23 in the UAE 25 processing

.and

words, the signal first comes in to poll the ninth group of elements 57 and the second (informational) inputs of which are connected to the corresponding (containing the sign code) leverage of register triggers 44, and writes this code to the input register of the unit 6 character generator. The next signal from the decoder 23 enters block 6 for switching on the character generator, i.e. to enable imaging of the corresponding character. After timing the sign mappings, the next signal passes from the decoder 23 to the counting input, for example, from the 5th bit of the counter X of the register 26 to move the beam to the next familiarity. After counting the time required to move the beam, the last signal of the sign program passes through the second group of elements OR 24 through the first VPSOD to the third element OR 30 and through the second inverter 29 to the installation of the counter 22 in O to activate the reading program from memory block 3 of the following words, and through the second output - to the installation of the next state on the first counter 4 addresses.

If the next word is signed, then its processing begins immediately, since the beam is already on the next familiarity. If the next word turns out to be coordinate, then its processing is performed as described above.

After reading the last word of the array from the memory block 3, with the End of the array sign, the signal from the decoder 23 passes to the interrogation of the eighth group of elements And 56 and after it goes to the installation of the Start trigger 20, then to the transition code line to set the program start code The end of the array to the counter 22, and to the installation of 1 flip-flop 60, the unit arm of which is connected to the first input of the fifth element And 61. The second input of this element receives the frequency, the third input is connected through a quarter-inverter 65 with the output of the seventh element And 64, which first counter connected to .6 so that the count of this counter 63 the time of about 20 ms (frequency of regeneration to generate an image on a sustainable

0876. 12

CRT screen) at the output of the seventh element And 64 appears low level which will block further passage of frequency through the sixth element And 62 to the input of the counter 63, and

simultaneously through the fourth inverter 65 comes as an enable signal to the third n of the element And 61. At this point, the word with

10 signs The end of the array is processed, i.e. the next display cycle is completed, the trigger 60 is 1, and from the output of the fifth element AND 61 the signal goes through the sixth element OR 66 and the fifth inverter 67 to the installation of the counter 63 in O (the frequency begins to arrive at it through the element 62), setting in On trigger 60 and on setting in 1

20 flip-flops 20. Now the counter 22 begins to receive the frequency again, and since its state corresponds to the first signal of the End of the Array program, then through a certain

5, the number of clock cycles, for example, 4, from the output of the decoder 23, a signal that comes from the first output of the control unit 1 to the installation in O of the first counter 4 and to the installation in O of the counter 22.

Thus, on the counter 22 (the state (O) is set corresponding to the first signal from the reading group of the new word, and on the first counter 4 is the code of the first cell, i.e. the new display cycle starts.

As was shown above, the device provides almost simultaneous cycles of exchange and display of information, with display priority prior to exchange when accessing memory block 3. This priority is provided by trigger 19, trigger 12 and other newly introduced elements. The trigger 19 is set to one state from the control unit 1 through the second element OR 17 and the first inverter 18 each time, until the end of the processing program of any word recorded on register 44, remains a time equal to the time of the exchange cycle. For example, if four beats are needed to carry out an exchange cycle, then in each group of signals that provide processing for the display of the corresponding words, there is a beat that is found. Edited by the last signal of the group in four cycles and connected to the input of the second element OR 17, whose output through the inverter 18 is connected to a single input, trigger 19, its setting is produced, for example, by analyzing the type of words coming from the decoder 23 to interrogation of the eighth group of elements And 56, i.e., then when the 3-memory block has completed a word reading cycle for display and can be used to conduct a write cycle from the digital computer until from the decoder 23 through the element OR 17 and Inverter 18 does not pass the signal is on e trig ger 19. The signal from its zero shoulder provided to a first input of the second AND gate 50 and blocks it at the input. The second input of the second element I 50 is connected to the frequency, and the third input is connected to the single output of trigger 49, which is controlled by a single input by the Begin Word and Beginning of Exchange signals coming from the 2-way communication unit 2. In exchange unit 2, control signals and code information are received from the digital computer, and the first group of amplifiers 32 is used to input signals such as Set to O, Start (trigger 20), Start of word, Start of exchange and signal of OBM signal to the device in the device about exchange (after each word is recorded). Signals The start of the word and the beginning of the exchange arrive at the corresponding inputs of the element OR 33 and pass through the inverter 34 to an installation in O register 35, information on which is recorded from a digital computer, for example, through a parallel code through the second group of amplifiers 36. Through amplifier 37 is entered into a digital computer the frequency to synchronize the exchange with the device. Information from certain bits of register 35 is fed to the information input of the fourth group of elements AND 15 (Starting address of the first cell of the exchange of memory block 3), and the output of each bit is connected to the input of the corresponding bit of register 38 via the fifth group of elements AND 41 , the fourth group of elements OR 40 and the second group of inverters 39. The signal to start the exchange sets the driver of 16 impulses to the state 1 trigger 54, and through the fifth element OR 47 and the third inverter 48 to the trigger O counts and 5. When a signal from the digital computer to exchange Start Register 35 records the management word containing the address of the first cell from which a subsequent array of information words is recorded in the memory unit 3. After trigger 49 is turned on, provided that trigger 19 is off, a second element 50 passes a signal that turns off trigger 49 and turns on trigger 51, the signal from the unit arm of which allows the frequency to go to the inputs of counter 53 and decoder 46, the signal from the output of the decoder 46 passes in this case (with the flip-flop 54 turned on) through the fourth element 55 and the control input of the fourth group of elements 15 and it writes the code of the first cell of the next exchange to the second counter 5. Then from the decoder 46 the signal End cycle about It is the exchange that sets the trigger 51 into О, the trigger 54 which is installed on the new input and passes into the exchange unit 2 via two-way communication. When this signal is received, the digital computer inputs the beginning of the word into the device, and then the first information word. This signal passes through a block of 2 .... °. 16 pulses for triggering the trigger 49. Assuming that the trigger 19 is off, the output of the second element I 50 is a signal that sets the trigger 49 in O and turns on the trigger 51, which allows the frequency to pass to the counter 53 and the decoder 46. Now ( when the trigger 54 is off, the signals from the output of the decoder 46 pass through a group of elements 45 to ensure the recording of information from register 35 to register 38 (from the second output of the driver 16 to the second input of register 13), overwriting the state of the second counter 5 to register 7 (with the first- output via the first OR gate 14 and a first group of AND gates 8) and incorporating mode recording in the block memory 3, then (via nekotorre time) to increase the state of the second counter 5 by one. The last signal from the decoder 46 sets in O the trigger 51 and

enters the exchange unit 2 as a signal. The end of the exchange cycle for requesting the next information word from a digital computer, etc.

If trigger 19 is turned on before trigger 49 is turned on, the exchange cycle does not start until trigger 19 is set to O.

If trigger 19 is turned on after trigger 49, the exchange cycle continues and ends normally. The moment the trigger 19 is turned on indicates that there are four clocks left before reading the memory block 3 to read a word to be displayed. Considering that the exchange cycle does not exceed four clock cycles, the trigger 19 does not allow instances of simultaneous access to the memory block 3 for display and exchange. As shown above., Trigger 12 operates synchronously with trigger 19, i.e. when reading

information from memory block 3 for mapping, the address register 7 records the state of the first counter 4 when there is a recording of information in memory block 3 from a digital computer to register 7

recording the state of the second counter 3.

Thus, the introduction of new blocks and communications into the proposed device ensures the creation of a stable non-blinking image on the video block screen when exchanging information with a digital computer and allows to increase its throughput compared to the known device.

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Claims (1)

A DEVICE FOR INFORMATION OUTPUT, containing the first and second counters, an exchange unit, a memory unit, a display unit and a control unit, the first output of which is connected to the input of the first counter, the second output to the Read memory unit input, the third output to the display unit input, the first input-output - with the control input-output of the exchange unit, the first information input-output of which is the information input-output of the device, characterized in that, in order to increase the throughput of the device, the first register is entered into it, first the first group of AND elements, the group of IDI elements, the second and third groups of AND elements, the first trigger, the register block, the first OR element, the fourth group of AND elements, the pulse shaper, the second trigger, the second OR element and the first inverter, the output of which is connected to the installation input in 1 of the second trigger, the input is connected to the output of the second OR element, the input of which is connected to the fourth output of the control unit, the fifth and sixth outputs of which are connected to the installation inputs in 1 and 0 of the first trigger, the seventh output is connected to the first input of the pulse driver, the eighth output is connected to the 0 input of the second trigger, the zero output of which is connected to the second input of the pulse shaper, the single output of the first trigger is connected to the first inputs of the AND elements of the second group, the second inputs of which are connected to the outputs of the first counter, and the outputs are connected with the first inputs of the elements OR groups, the second inputs of which are connected to the outputs of the elements of the third group, and the output is connected to one inputs of the elements of the first group, the other inputs of which are connected to the output of the first OR element, and the outputs with the inputs of the first register, the outputs of which are connected to the address inputs of the memory block, the input-output of which is connected to the first input-output of the register block, and the Record input is connected to the first output of the pulse shaper and to the first input of the first OR element, the second input of which is connected to the second output of the control unit, the second input - · the output of which is connected to the second input-output of the register block, the first information input of which is connected to the first output of the Exchange unit, the second information input is connected is connected to the second output of the pulse generator, the second information input-output of which is connected to the second information input-output of the exchange unit, the third output is connected to the counting input & h of the second counter, the fourth output to one inputs of elements And the fourth group, the other inputs of which are connected to the second output of the exchange unit, and the outputs - with the inputs of the parallel input of the second counter, the output of which is connected to the first input _{# of} the third group of AND elements, the second input of which is connected to the zero output of the first trigger.