SU1288705A1

SU1288705A1 - Device for allocating memory resources in computer complex

Info

Publication number: SU1288705A1
Application number: SU853874926A
Authority: SU
Inventors: Вячеслав Вячеславович Мазаник
Original assignee: Войсковая часть 03080
Priority date: 1985-03-22
Filing date: 1985-03-22
Publication date: 1987-02-07

Abstract

Изобретение относитс к области вычислительной техники, в частности к устройствам управлени , и может быть использовано дл управлени многобуферным обменом в вычислительных комплексах. Целью изобретени вл етс расширение функциональных возможностей за счет управлени многобуферным обменом в вычислительных комплексах. Устройство содержит генератор импульсов, счетчик, блок пам ти , коммутатор, с первого по третий дешифраторы, с первого по третий регистры, первый и второй триггеры, группу счетчиков, формирователь импульсов , элемент запрета, первый и второй элементы задержки, первый и второй блоки элементов ИЛИ, с первого по четвертый блоки элементов И, первый и второй элементы И, группу блоков элементов И. Устройство осуществл ет аппаратную переадресацию пйм ти, образу адрес из номера блока пам ти и дескриптора адреса. 1 ил. (Л 00 The invention relates to the field of computing, in particular, to control devices, and can be used to control multi-buffer exchange in computer complexes. The aim of the invention is to expand the functionality by controlling multi-buffer exchange in computing systems. The device contains a pulse generator, a counter, a memory unit, a switchboard, first to third decoders, first to third registers, first and second triggers, a group of counters, a pulse shaper, a prohibition element, first and second delay elements, first and second blocks of elements OR, the first to fourth blocks of the AND elements, the first and second elements of AND, a group of blocks of the elements of I. The device performs hardware forwarding of the letter, forming the address from the memory block number and the address descriptor. 1 il. (L 00

Description

Изобретение относитс к вычислительной технике, в частности к устройствам управлени , и может быть использовано дл управлени многобуферным обменом с пам тью в вычислительных 5 комплексах.The invention relates to computing, in particular, to control devices, and can be used to control multi-buffer exchange with memory in computing 5 complexes.

Цель изобретени - расширение функциональных возможностей за счет управлени буферным обменом в вычислительном комплексе.The purpose of the invention is to expand the functionality by controlling the buffer exchange in the computing complex.

На чертеже представлена структурна схема устройства.The drawing shows a block diagram of the device.

Устройство содержит генератор 1 импульсов , счетчик 2, блок 3 пам ти, коммутатор 4, первый 5, второй 6, и третий 7 дешифраторы, первый 8, второй 9 и третий 10 регистры, пер- вьй 11 и второй 12 триггеры, группу счетчиков 13, формирователь 14 им15The device contains a pulse generator 1, counter 2, memory block 3, switch 4, first 5, second 6, and third 7 decoders, first 8, second 9 and third 10 registers, first 11 and second 12 triggers, group of counters 13 shaper 14 im15

состо ние. При этом на выходе дешифратора 5 по вл етс сигнал, который разрешает подключение инверсных вьгходов j-ro счетчика 13 к второму входу j-ro блока 26 элементов И. Если j-й счетчик 13 находитс в нулевом состо нии, то на выходе формировател 14 по вл етс сигнал, который разрешает выдачу кода номера j блока из j-ro регистра 29 в регистр 10 (код младших разр дов дискрипто- ра), а затем вьщачу кода дискрипто- ра из регистров 9 и 10 на вход 35 ВК. При этом также регистры 8-10, триггеры 11 и 12 и счетчик 2 устанавливаютс в нулевое состо ние, сигнал с выхода элемента 17 задержки поступает на вход готовности ВК, содержимое j-ro счетчика 13 увеличивает25condition. At the same time, a signal appears at the output of the decoder 5, which permits the connection of inverse inlets of the j-ro of the counter 13 to the second input of the j-ro of the 26-unit I. If the j-th counter 13 is in the zero state, then the output of the former 14 is is a signal that allows the issuance of the code number j of the block from the j-ro register 29 to register 10 (code of the lower bits of the cryptograph), and then the code of the cryptograph from registers 9 and 10 to the input 35 of the VK. At the same time, registers 8-10, triggers 11 and 12 and counter 2 are set to the zero state, the signal from the output of the delay element 17 is fed to the VC ready input, the contents of the j-ro counter 13 increases25

пульсов, элемент 15 запрета, первый с на единицу, т.е. j-й буфер за- и второй 17 элементы задержки, пер- хватываетс дл обмена, вый 18 и второй 19 блоки элементов Если содержимое j-ro счетчика 13 ИЛИ, первьш 20, второй 21, третий 22 и четвертый 23 блоки элементов И, первый 24 и второй 25 элементы И, первую 26 и вторую 27 группы блоков элементов И, блок 28 элементов ИЛИ, Ьлок 29 регистров, выход 30 задани номера блока вычислительного комплекса , выход 31 старших разр дов дискриптора вычислительного комплекса , выход 32 запуска вычислительного комплекса, выход 33 кода открепленного буфера вычислительного комплекса , выход 34 младших разр дов дискриптора -вычислительного комплекса, вход 35 младших разр дов дискриптора вычислительного комплекса, вход 36 готовности вычислительного комплек30pulses, prohibition element 15, the first one per unit, i.e. The j-th buffer is the second and second 17 delay elements, it is picked up for the exchange, the left 18 and second 19 blocks of elements If the contents of the j-ro counter are 13 OR, the first 20, the second 21, the third 22 and the fourth 23 blocks of elements And, the first 24 and second 25 elements And, the first 26 and second 27 groups of blocks of elements And, block 28 elements OR, block 29 registers, output 30 specifying the number of the block of the computing complex, output 31 of the higher bits of the computing complex of the computing complex, output 32 of starting the computing complex, output 33 codes of the detached buffer of the computing complex, d 34 low-order bits of the descriptor-computing complex, input 35 low-order bits of the computing complex of the computing complex, input 36 of the readiness of the computing complex

3535

не равно нулю, то нулевой сигнал с выхода формировател 14 разрешает прохождение задержанного элементом 16 импульса запуска через элемент 15 запрета и установку в единичное состо ние триггера 12. При этом с помощью счетчика 2 и генератора 1 проводитс последовательный анализ содержимого счетчиков 13 до тех пор, пока не найден i-й счетчик 13, содержимое которого равно нулю. Далее работа устройства аналогична процессу , описанному дл случа j-ro счетчика 13.not zero, the zero signal from the output of the former 14 permits the launch pulse delayed by the element 16 to pass through the prohibition element 15 and the trigger 12 is set to one. At the same time, using the counter 2 and the generator 1, the contents of the counters 13 are sequentially analyzed until the i-th counter 13 is found, the content of which is zero. Further, the operation of the device is similar to the process described for the case of the j-ro counter 13.

рует в качестве результата дискрип- тор с соответствующим математическимas a result, the disc with the corresponding mathematical

Claims

Invention Formula

From the output of 33 VC, the impulse code i of the number of the detached

sa; The input is from 7 higher bits of the de squeak-40 buffer, resulting in the bth counter of the computer complex. Y eats.

Thus, the device device operates as follows.

In the initial state, the registers 8-45 with the address describing the information 10, the triggers 11 and 12, the counter 2 are zeroed out for the buffer exchange, lena, the registers 29 store the codes of the block numbers, the i-th (, p) counter 13 zero if i-th buffer is not in exchange. 50

From the output 30 of the computing complex (VC) to the register 8, the code j of the block number is written (the parameter of the write operation or reading in the multi-buffer exchange), from the output 31 of the VC to the register 9 the code of the higher bits of the descriptor is written; sets trigger 11 to a single

A device for allocating memory resources in a computing complex, contents (its counter, first decoder, memory block, switch, pulse generator, first trigger, first and second blocks of AND elements, group of counters, first register, first block of OR elements , the first element And, a group of blocks of elements And, and the input of the lower bits of the form

condition. At the same time, a signal appears at the output of the decoder 5, which permits the connection of inverse inlets of the j-ro of the counter 13 to the second input of the j-ro of the 26-unit I. If the j-th counter 13 is in the zero state, then the output of the former 14 is is a signal that allows the issuance of the code number j of the block from the j-ro register 29 to register 10 (code of the lower bits of the cryptograph), and then the code of the cryptograph from registers 9 and 10 to the input 35 of the VK. At the same time, registers 8-10, triggers 11 and 12 and counter 2 are set to the zero state, the signal from the output of the delay element 17 is fed to the VC ready input, the contents of the j-ro counter 13 are increased by one, i.e. The jth buffer is captured for the exchange. If the contents of the j-ro counter are 13

with per unit, i.e. The jth buffer is captured for the exchange. If the contents of the j-ro counter are 13

not zero, the zero signal from the output of the former 14 permits the launch pulse delayed by the element 16 to pass through the prohibition element 15 and the trigger 12 is set to one. At the same time, using the counter 2 and the generator 1, the contents of the counters 13 are sequentially analyzed until the i-th counter 13 is found, the content of which is zero. Further, the operation of the device is similar to the process described for the case of the j-ro counter 13.

as a result, the disc with the corresponding mathematical

Invention Formula

an address describing the information part of the buffer exchange,

A device for allocating memory resources in a computing complex, contents (its counter, first decoder, memory block, switch, pulse generator, first trigger, first and second blocks of AND elements, group of counters, first register, first block of OR elements, the first element And, a group of blocks of elements And, and the input of the lower bits of the descriptor

the device memory is connected to the information input of the memory unit whose output is connected to the information input of the switch, the first, second inputs and output of the first element I are connected respectively to the outputs of the first trigger, pulse generator and the counting input of the counter; to the information input of the first register, characterized in that, in order to expand the functionality by controlling the buffer exchange in the computer complex, the second and third decryption are introduced tori, second and third registers, second trigger, pulse shaper, prohibition element, first and second delay elements, second block of RShI elements, third and fourth block of And elements, second And element, with the output of the first block of And elements connected to the input of the first decoder, the output of the first register is connected to the first input of the first

block of elements And, the output of which

connected to the first input of the first block of elements OR, the device start input is connected to the single input of the second trigger and to the input of the first delay element whose output is connected to the information input of the prohibition element, the higher bits of the device’s memory descriptor are connected to the information input of the second register, the output which is connected to the first input of the second block of elements I, the output of which is connected to the output of the higher bits of the device’s memory descriptor, the output of the pulse former is connected to the input of the second first element of the delay, to the first inputs of the third and fourth blocks

5 o 5 0

0 5

five

And elements, to the second input of the second block of And elements, to the control input of the switch and to the control input of the prohibition element, the output of which is connected to the single input of the first trigger, the output of the second delay element is connected to the reset inputs of the counter, first, second and third registers, the first and second triggers and to the device ready output, the output of the counter is connected to the second input of the first block OR, the output of the third register is connected to the second input of the third block of elements AND whose output is connected to the input m low bits of the device memory descriptor, the device mask mask code input is connected to the second decoder input, the outputs of which are connected to the reset inputs. the corresponding group counters, -Inverse outputs of which are connected to the first inputs of the corresponding blocks of elements AND groups, the second inputs of which are connected to the outputs of the first decoder, the outputs of the blocks of elements and groups are connected to the inputs of the second block of elements OR, the output of which is connected to the corresponding input of the second element AND, the output of which is connected to the input of the pulse former, the output of the switch is connected to the information input of the third register and to the second input of the fourth block of elements I, the output of which one with the input of the third decoder, the outputs of which are connected to the counting inputs of the corresponding group counters, the output of the first decoder is connected to the second information input of the switch, the output of the second trigger is connected to the second input of the first block of elements I.

Jj