SU881722A1 - Interface - Google Patents

Description

(54) DEVICE FOR PAIRING

R

The invention relates to automation and computing, and can be used to interface two data processing devices of different speeds.

Known devices for; interfaces containing a buffer memory in registers, input and output switches, distributors for input and output of information, register of labels, adder, two comparison circuits, two registers of constants and a control node til.

The disadvantage of these devices is their complexity and high hardware costs.

Closest to the invention, in essence, is an interface device containing a buffer memory, the information inputs of which are information inputs of the device, the control input through the recording stub element connected to the recording control input of the device, the first input

the trigger, the input of the write counter and the first count input of the reversible counter, the second count input of which is connected to the input of the read counter, the read control input, the second trigger input, and the read delay element with the control input of the output switch whose outputs are device information outputs , but

10 inputs - connected to the information outputs of the buffer memory, whose address input is connected to the output of the address switch, the first and second inputs of which are connected respectively to the outputs of the write counter and read counter, the control inputs to the corresponding trigger outputs, and the lock input. the output of the decoder is zero, the input

20 connected to the output of the reversible counter C2j.

Claims (2)

The disadvantage of this device is its low throughput capacity, which is caused by the impossibility of simultaneous eapie and readout of the buffer memory. The purpose of the invention is to increase the capacity of the device. The goal is achieved by the fact that, in the device containing the buffer memory, the outputs connected to the corresponding information inputs of the information output switch, the output of which is the information output of the device, the recording counter connected to the control input of the recording device and the first input of the reversible counter The second INPUT of which is connected to the control input of the readout of the device and the input of the readout counter, and the output through the first decoder g with the output of the read permission of the device, you One readout counter is connected to the address input of the information output switchboard, the information input switchboard and the second decoder are entered, the output of the reversible counter is connected via the second decoder to the write enable output of the device, the input of the information input switch is connected to the information input of the device, and information outputs to the corresponding inputs of the buffer memory. The drawing shows the block diagram of the device. The device contains information source 1, write counter 2, information input switch 3, buffer memory registers 4, read counter 6, information output switch 7, information receiver 8, second decoder 9, reversible counter 10, first decoder 11, input 12 p The terminal 8, the input 13 of the source. The device works in the following way. Before the process of transmitting a sequence of discrete signals, source 1 sends a request to receive signal at input 12 of receiver 8. At .11, a receiver 8 sends a signal to input signal 13 of source 1 and is ready to receive. After that, source 1 generates a sequence of codes that arrive at the input of switch 3. At the same time, each signal of the sequence accompanies a clock pulse jiocTynaeT on counter 2, which gives addresses for connecting the input 3 of switch 3 to the corresponding register A of buffer memory 5. arrive at the input -and reversible counter. fO. The capacity of the reversible counter 10 corresponds to the number of registers 4 of buffer memory 5. Reversible counter 10 has parallel outputs (from each bit), which are connected to the corresponding inputs of decoders 9 and 11. Simultaneously with recording the first signal, the sequence, i.e. with the advent of the first clock pulse, "and the output of the decoder I1, a signal is generated. The information is written into a buffer memory, which allows the receiver 8 to read the information. 8 discrete signals at the receiver input synchronously with read pulses. The counter 6 together with the switch 7 operates in such a way that the reading of signals occurs in the same way as their recording order. At the same time, the pulses are fed to the input -1 | of the counter counter 10, so that each of these pulses reduces the contents of the reversing counter by one pulse. Thus, in the process of writing and reading, a number of pulses is stored in the reversible counter 10, equal to the number of memory registers A 5, which still contain unread information. Since writing and reading occur at different speeds, it may happen that there will not be a free register in the buffer memory 5 to write the subsequent code. This moment is determined by the decoder 9, which generates a write blocking signal, which is fed to the corresponding input of source 1 and prohibits the sending of codes to the input of switch 3 and the corresponding write clock. After the release of at least one register A, the decoder 9 removes the blocking signal, and the recording will be continued into the free registers, i.e. In registers, in which information was read. If reading is faster than writing, then in the zero state of the reversible counter 10 of the decoder 58, the torus 11 outputs to the receiver 8 a read lock signal that will be held until one register is filled. Thus, the invention provides simultaneous recording and reading of information from the buffer memory, which leads to an increase in its throughput. Claims An interface device containing a buffer memory, outputs connected to the corresponding information inputs of an information output switch, the output of which is the information output of the device, a record counter connected to the control input of the record of the device and the first input of the reversible counter, the second input of which connected to the control of the read input of the device and the read counter input of the output through the first decoder with the read enable output of the device, the output of the account A read switch is connected to the address input of the information output switch, which is different from the fact that, in order to increase the throughput of the device, an information input switch and a second decoder are entered into it, and the output of the reversible counter through the second decoder is connected to the write enable output of the device, the input The information input switch is connected to the information input of the device, the address input to the output of the record counter, and the information outputs to the corresponding inputs of the buffer memory. Sources of information taken into account in the examination 1. The copyright certificate. USSR № 602934, cl. G 06 F 3/04, 1975. 2. USSR author's certificate for application number 2651507 / 18-24, cl. G 06 F 3/04, 1978 (prototype).