JP2699482B2 - Data transfer control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is used for an information processing apparatus. The present invention relates to a data transfer control device that performs data transfer control.

〔Overview〕

The present invention relates to a data transfer interface for transferring data from a partially writable interface to a partially writable interface. In the data transfer interface, when all the transmitted data is valid, the data is transferred as it is, and when the data is partially valid, the byte position is changed. By performing an address value calculation based on mask information and designating a local memory to perform data writing and reading, data transfer can be performed with a small hardware configuration and simple control. is there.

[Conventional technology]

When transferring data from a partially writable interface to a partially writable interface, data transferred from the middle of a word on the partially writable interface must be transferred from the beginning of the word on the partially writable interface. There must be. For example, there is a case where valid data is transferred from the lower byte of the first word when the interface capable of partial writing is 2 bytes. At this time, assuming that the interface for which partial writing is not possible is also 2 bytes, when transmitting to this interface, valid data must be transmitted from the upper part of the first word.

Conventionally, after data to be received is stored in two registers for data transfer in the data transfer device for two words, the lower one byte of the first data transfer register is transferred to the upper one byte of the local memory. The upper 1 byte data of the second data transfer register is transferred to the lower 1 byte of the local memory.
And stores the next one word of data in the first data transfer register, and then transfers the lower one byte of the second data transfer register to the upper one byte of the local memory. The upper 1 byte of the first data transfer register is transferred to the lower 1 byte of the local memory and stored. Thereafter, data is stored in the local memory by alternately using the first and second data transfer registers of two words to store data, and this data is directly transmitted to an interface in which partial writing is not possible to transfer data. Had gone.

[Problems to be solved by the invention]

In the above-described conventional data transfer device, when data is transferred from a partially writable interface to a partially non-writable interface, the former has two words of registers and the data from the system memory is alternately written to those registers. Since the data transfer is performed by receiving the data, the hardware becomes large and the control becomes complicated.

An object of the present invention is to provide an apparatus which can eliminate such disadvantages and can transfer data from an interface capable of partially writing to an interface capable of partially writing with a simple circuit and with a simple control. And

[Means for solving the problem]

The present invention is directed to a local memory unit that is connected to a first interface that can be partially written as a transfer source and a second interface that cannot be partially written as a transfer destination, and temporarily stores data transferred from the first interface. A data transfer control device comprising: an address unit for generating an address of the local memory unit; and a mask storage unit for storing a mask state input to the first interface, wherein the local memory units are equivalent in parallel. A memory having a capacity is arranged, and a data handling unit for distributing the first interface to the memory arranged in parallel according to the contents of the mask storage unit is provided in the local memory unit, and the address unit is provided in the mask storage unit. Means for calculating an address to be given to the memory unit according to the contents. And wherein the Mukoto.

[Action]

When valid data and mask information indicating the valid data are transmitted from the upper byte and the lower byte of the first word of the partial writable interface, the mask storage unit stores the mask information, and the address operation unit stores the address information in the address unit. Is sent as it is, and data is temporarily written in the local memory unit. When writing of all data is completed, the data is sent to the partially writable interface.

When valid data and mask information indicating only valid data from the lower byte to the lower byte of the first word of the partial write disable interface are transmitted, the mask storage unit stores the mask information and the data handling unit stores the mask information as the upper byte. Invert the lower byte. At this time, the address calculation unit calculates and sends the data in the address portion,
The transmitted data is temporarily written in a local memory unit determined by the operation, and when all the data has been written, the data is sent to the partial write disable interface.

As a result, data can be transferred from a partially writable interface to a partially non-writable interface with a small circuit configuration and simple control.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings. First
FIG. 2 is a block diagram showing the configuration of the embodiment of the present invention.

In the embodiment of the present invention, the local memory unit 5 is connected to the partial write enable interface 2 as the transfer source and the partial write disable interface 3 as the transfer destination, and temporarily stores the data transferred from the partial write enable interface 2. , 6 and an address unit 7 and an address operation unit 8 which constitute address means for generating addresses of the local memory units 5, 6.
A feature of the present invention is to provide a mask storage unit 12 for storing a mask state input to the partial writable interface 2, and the local memory units 5 and 6 have memories of the same capacity arranged in parallel. Part 5,
6 is provided with a data handling unit 4 for distributing a partial writable interface to memories arranged in parallel in accordance with the contents of a mask storage unit 12, and an address unit 7 and an address calculation unit 8 constituting address means are provided in a mask storage unit. Local memory units 5 and 6 according to contents of 12
Means for calculating the address given to

The local memory units 5 and 6 are connected to a partially writable interface driver 11, to which the partially writable interface 3 is connected.

The operation of the embodiment of the present invention thus configured will be described.

First, the first of the partially writable interface 2
Consider a case where data transfer is performed from the upper byte of a word. In this case, if the data transfer is 2 bytes or more,
Since the first word is valid data in both the upper and lower bytes, mask information indicating the data is sent together with the data.

The data transfer control device 1 stores the mask information of the first word in the mask storage unit 12 and, since both bytes are valid, the partial write enable interface 2
Is transferred to the local memory unit 6 and the lower one byte is transferred to the local memory unit 5. At this time, since the data of the partially writable interface 2 is both valid, the address operation unit 8 sends the data of the address unit 7 to the local memory lower address line 9 as it is. Here, a write pulse is output to the local memories 5 and 6 to perform writing, and the address section 7 is written.
Is incremented by 2 bytes.

Then, when the next word is sent, the mask storage
Since it is stored in step 12 that the first word is valid for both bytes, it is written to the local memories 5 and 6 in the same procedure as described above. Similarly, data is written to the local memories 5 and 6 until the last byte.

When the writing of all the data to the local memories 5 and 6 is completed, the data is sent from the partially writable interface driver 11 to the partially writable interface 3 next. This is local memory 5
And the lower byte of the local memory 5 is transmitted from the partial write disable interface driver 11 to the lower side of the partial write disable interface 3 to the upper byte of the partial write disable interface 3. To complete the transfer. This state is shown in FIG.

Next, the first of the partially writable interface 2
Consider a case where data transfer is performed from the lower byte of a word. In this case, since the first word is valid data only in the lower byte, mask information indicating the data is sent together with the data. Then, the data transfer control device 1
Since the mask information of the word is stored in the mask storage unit 12 and only the lower byte is valid, the data handling unit 4 inverts the upper byte and the lower byte, and transfers the upper byte of the partial writable interface 2 to the local memory unit 5 as the lower byte. Is transferred to the local memory unit 6. At this time, since only the lower byte of the data of the partial writable interface 2 is valid, the address operation unit 8 subtracts one byte of the data of the address unit 7 and sends it to the lower address line 9 of the local memory. here,
A write pulse is issued to the local memories 5 and 6 to perform writing, and the address section 7 is incremented by 2 bytes.

Then, when the next word is sent, the mask storage
In step 12, since the first word stores that only the lower 1 byte is valid, it is written to the local memory in the same procedure as described above. Similarly, data is written to the local memories 5 and 6 until the last byte. When all the data has been written to the local memories 5 and 6, the data is sent to the partial write disable interface 3. This means that the upper byte of the local memory is sent out to the upper side of the interface and the lower byte of the local memory is sent out to the lower side of the partially writable interface 3 from the partially writable driver 11 in the order of writing to the local memories 5 and 6. This completes the transfer. This state is the third
Shown in the figure.

〔The invention's effect〕

As described above, according to the present invention, there is an effect that data can be transferred from an interface where partial writing is possible to an interface where partial writing is not possible with a small circuit configuration and simple control.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a diagram showing an example of data transfer in a case where both first bytes are valid data in the embodiment of the present invention. FIG. 3 is a diagram showing an example of data transfer when the first word is valid data only in the lower 1 byte in the embodiment of the present invention. 1 ... Data transfer control device, 2 ... Partial writable interface, 3 ... Partial writable interface, 4 ... Data handling unit, 5 ... Local memory (lower 1 byte), 6 ... Local memory (higher order) 7) Address part, 8 ... Address operation part, 9 ... Local memory lower address line,
10: Upper address line of local memory, 11: Partial write disable interface driver, 12:
Mask storage unit.

Claims (1)

(57) [Claims] A local memory connected to a first interface capable of partial writing as a transfer source and a second interface non-partial writable as a transfer destination and temporarily storing data transferred from the first interface. A data transfer control device comprising: a memory unit that stores a mask state input to the first interface; wherein the local memory unit is provided in parallel with the local memory unit. A memory having an equivalent capacity, a data handling unit for distributing the first interface to memories arranged in parallel according to the contents of the mask storage unit in the local memory unit, and the address unit includes a mask storage unit Calculate the address given to the memory unit according to the contents of A data transfer control device comprising means.