JPH06208539A - High-speed data transfer system - Google Patents

Abstract

PURPOSE:To transfer words at a high speed without any loss of transfer time by segmenting a normal access and a high-speed data transfer space with addresses and adding an address selector and a control circuit to a storage device. CONSTITUTION:A processor 1 writes a base address, given to a storage device 3 at a transfer destination, in a base address register 5 and outputs an address to an address bus 1a. An address decoder 4 decodes the address and when the decoding result indicates high-speed data transfer from a storage device 2 to the storage device 3, that is reported to the address selector 6 and a high- speed data transfer control circuit 7. The address selector 6 outputs the base address to the storage device 3. A high-speed data transfer control circuit 7 calculates the offset value of the normal access space and calculates an address in the high-speed space from the value. The storage device 2 reads only data to be transferred out of the address and then the data in the storage device 2 are transferred to the specific address in the storage device 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed data transfer system, and more particularly to a high-speed data transfer system for performing high-speed block transfer between different storage devices such as when transferring image data on a main memory to a display memory.

[0002]

2. Description of the Related Art Conventionally, a high-speed data transfer system of this type uses a DMA control circuit which separates a processor from a memory bus at the time of data transfer and generates a transfer address and a transfer timing instead of the processor.

[0003]

The above-mentioned conventional high-speed data transfer system has a problem that an arbitration circuit is necessary because the data is separated from the processor at the time of transfer.
Further, there is a problem that time is lost due to the arbitration.

There is also a problem that a register for setting a transfer address and counting up for each word transfer, a counter, an interface circuit for notifying the processor of transfer completion, etc. are required. So there is a problem of doing.

[0005]

A high-speed data transfer system of the present invention includes a processor having a function of outputting a base address and an address to control the system, an address bus connected to the processor to send an address, A data bus connected to the processor for sending data, a first storage device connected to the address bus and the data bus, and a second storage device connected to the address bus and the data bus, A base address register for storing a base address to be given to the second storage device as a high-order address at the time of high-speed data transfer, and the first, first if the result of decoding the address from the processor is a normal access space. The high-speed data transfer space access is the result of decoding by applying a selection signal to either one of the two storage devices. Wherein in case of Tsu first, an address decoder indicates that it is the second storage device both in the same time high-speed data transfer space access gives a selection signal,
When the output of the base address register and the address of the corresponding bit position from the address bus are input and the notification from the address decoder is normally accessed, the address bus side is selected and the upper address is stored in the second storage device. And an address selector for selecting an address on the side of the base address register and supplying the same to the second memory device as a higher-order address during high-speed data transfer, and using the second memory device as the transfer source from the address decoder. When a high-speed data transfer is notified, an address to be read is calculated from the base address, and only the data to be transferred is read from the address in which the transfer source data is stored and transferred to the first storage device. If the first storage device is the transfer source, the address written in the second storage device is used as the base. And a high-speed data transfer control circuit for transferring the read data is calculated from the address from the first storage device.

[0006]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of the present invention.

The high-speed data transfer system shown in FIG. 1 includes a processor 1 having a function of outputting a base address and an address to control the system, an address bus 1a connected to the processor 1 to send an address, and the processor 1. A data bus 1b which is connected and sends out data; a storage device 2 which is connected to the address bus 1a and the data bus 1b;
A storage device 3 connected to the address bus 1a and the data bus 1b, a base address register 5 for storing a base address given to the storage device 3 as a higher-order address during high-speed data transfer, and a result obtained by decoding the address from the processor 1. Is a normal access space, a selection signal is given to either one of the storage devices 2 and 3 and the result of decoding is high-speed data transfer space access, both storage devices 2 and 3 are selected. An address decoder 4 which gives a signal to simultaneously notify the high-speed data transfer space access, and the output from the base address register 5 and the address of the corresponding bit position from the address bus 1a are input to notify from the address decoder 4. Selects the address bus 1a side at the time of normal access and sets it as the upper address to the storage device 3. Storage device by selecting the address of the base address register 5 side at the time of high-speed data transfer paper to 3
An address selector 6 supplied as an upper address to
When the address decoder 4 gives a notification of high-speed data transfer from the storage device 3 as the transfer source, the read address is calculated from the base address and the transfer data is read from the stored address. Transfer to the storage device 2, and if the storage device 2 is the transfer source, the storage device 3
And a high-speed data transfer control circuit 7 which transfers the data read from the storage device 2 by calculating the write address from the base address.

FIG. 2 is a block diagram illustrating the function of the high speed data transfer control circuit shown in FIG. The high-speed data transfer control circuit 7 refers to the address map 20 using the memory devices 2 and 3 as one memory device having different addresses, and refers to the address map 20 by the data from the address decoder 4 to transfer the data from the memory device 2 to the memory device 3. Data transfer determination unit 70 that determines whether the transfer is from the storage device 3 to the storage device 2, the normal data transfer, or the high-speed data transfer, and the data transfer determination unit 70 is the transfer from the storage device 2 to the storage device 3. If determined, the offset value calculation unit 71 that calculates the offset value from the relative address between the head of the data stored in the storage device 2 and the head of the normal access space in the address map 20, and the offset value calculation unit 71 calculated. From the offset value, the relative address is added to the start address of the high speed data transfer space of the storage device 2 in the address map 20. By doing so, if the offset address calculation unit 72 that calculates an address in the high-speed address space and the data transfer determination unit 70 determine that the transfer is from the storage device 3 to the storage device 2, the data is stored in the storage device 3 in the address map 20. An offset value calculation unit 73 that calculates an offset value from the relative address between the start of the stored data and the start of the normal access space of the storage device 3, and the address map 20 for the relative address from the offset value calculated by the offset value calculation unit 73. In the storage device 2, the offset address calculation unit 74 that calculates the address in the high-speed address space by adding it to the start address of the high-speed data transfer space, and the addresses calculated by the offset address calculation units 72 and 74 are notified to the storage device 2. And an address notifying section 75 for controlling the address.

FIG. 3 is a structural diagram of an address map of the high speed data transfer control circuit shown in FIG. The addresses of the embodiment are the normal access space 21 for normal access of the storage device 2, the normal access space 22 for normal access of the storage device 3, and the high-speed data transfer space 23 for high-speed data transfer of the storage device 2. , A high-speed data transfer space 24 for high-speed data transfer of the storage device 3, and one-to-one with each other.
Is mapped to.

Next, the operation of the present invention will be described with reference to the drawings with reference to the case of performing high-speed data transfer from the storage device 2 to the storage device 3. The processor 1 writes the base address given to the storage device 3 of the transfer destination to the base address register 5 via the data bus 1b, and the address bus 1
Output the address to a. If the address decoder 4 decodes and the result is high-speed data transfer from the storage device 2 to the storage device 3, the address decoder 4 notifies the address selector 6 and the high-speed data transfer control circuit 7 of it. The address selector 6 outputs the base address to the storage device 3. In the high-speed data transfer control circuit 7, the data transfer judgment unit 70 makes a judgment, and the offset value calculation unit 71 calculates the offset value in the normal access space 21. The offset address calculation unit 72 adds the relative address portion from the offset value to the start address of the high-speed data transfer space 23, so that the high-speed address space 2 to be read at the time of high-speed transfer.
The address in 3 is calculated. The address notification unit 74 notifies the storage device 2 of the address. The storage device 2 reads only the data to be transferred from the address notified by the address notification unit 74. By this read operation, the data in the storage device 2 is transferred to the address designated by the base register 5 of the storage device 3.

Next, the case of performing high-speed data transfer from the storage device 3 to the storage device 2 will be described. Processor 1
Writes the base address given to the storage device 3 of the transfer source to the base address register 5, outputs the address, and the address decoder 4 decodes the result, and the result is the storage device 3
If it is a high-speed data transfer from the memory device 2 to the storage device 2, the address decoder 4 notifies the address selector 6 and the high-speed data transfer control circuit 7 of it. The contents of the base address register 5 are notified to the storage device 3 via the address selector 6, and the storage device 3 reads only the data to be transferred from that address and the address from the processor 1. In the high-speed data transfer control circuit 7, the data transfer judgment unit 70 makes a judgment, and the offset value calculation unit 73 calculates an offset value from the relative address between the head of the transfer source data and the head of the normal access space 21. The offset address calculation unit 74 calculates the address in the high-speed high-speed data transfer space 23 to be written at the high-speed transfer by adding the relative address from the offset value to the start address of the high-speed data transfer space 23. The address notification unit 75 notifies the storage device 2 of the address. As a result, the data of the storage device 3 read at the base address is transferred to the address of the storage device 2.

FIG. 4 is a block diagram showing a second embodiment of the present invention. In this embodiment, the processor 1 of the first embodiment is the processor 11, the base register 5 is the offset register 15, and the address selector 6 is the address bus 1.
The connection with a is eliminated and replaced with the mask gate 16, and the output of the mask gate 16 and the address on the address bus 1a are connected to the address adder 17. The offset register 15 stores the offset value added to the address on the address bus 1a during the high speed data transfer from the processor 11. The mask gate 16 outputs the value of the offset register 15 when the high-speed transfer space access is notified from the address decoder 4, and outputs "0" in the normal access space. Address adder 1
7 is an offset register 1 through the mask gate 16
The value of 5 and the address on the address bus 1a are added and the result is supplied as the address of the storage device 3. The processor 11 has a function of outputting an offset value.

Next, the operation of the present invention will be described with reference to the drawings and the case of transferring from the storage device 2 to the storage device 3. The processor 11 writes the offset value given to the transfer destination storage device 3 into the offset register 15,
The address is output to the address path 1a. If the address decoder 4 decodes and the result is high-speed data transfer from the memory device 2 to the memory device 3, the address decoder 4 notifies the mask gate 16 and the high-speed data transfer control circuit 7 of it. The mask gate 16 notifies the address adder 17 of the offset value. The address adder 17 adds the value of the data bus 1b and the offset value, and the storage device 3
The address to which the data in the storage device 2 is transferred is calculated. The high-speed data transfer control circuit 7 includes a data transfer determination unit 7
0 determines that the offset value calculation unit 73 calculates the offset value, and the offset address calculation unit 74 calculates the address in the high-speed data transfer space 23. Address notification unit 7
5 notifies the storage device 2 of the address. This allows
The data in the storage device 2 is the address adder 1 of the storage device 3.
7 to the address via 7.

Next, the case of transferring from the storage device 3 to the storage device 2 will be described. The processor 11 writes the offset value given to the storage device 3 of the transfer source into the offset register 15 and outputs the address to the address path 1a. If the address decoder 4 decodes and the result is high-speed data transfer from the memory device 3 to the memory device 2, the address decoder 4 notifies the mask gate 16 and the high-speed data transfer control circuit 7 of it. The mask gate 16 notifies the address adder 17 of the offset value. The address adder 17 adds the value of the data bus 1b and the offset value and notifies the storage device 3 that the storage device 3 reads only the data to be transferred from the address. In the high-speed data transfer control circuit 7, the data transfer judgment unit 70 makes a judgment, the offset value calculation unit 73 calculates an offset value, the offset address calculation unit 74 calculates an address in the high-speed data transfer space 23, and the address notification unit. 75 stores address 2
To notify. As a result, the data of the storage device 3 read at the base address is transferred to the address of the storage device 2.

[0016]

As described above, according to the present invention, a processor having a function of outputting a base address and an address to control the system, an address bus connected to the processor to send out an address, and a processor connected to the processor are connected. A data bus for transmitting data, an address bus, a first memory device connected to the data bus, a second memory device connected to the address bus, data bus, and a second memory device during high-speed data transfer. A base address register that stores the base address given to the device as a higher-order address, and if the result of decoding the address from the processor is the normal access space, select either one of the first and second storage devices. If the result of applying a signal and decoding is a high-speed data transfer space access, it is selected for both the first and second storage devices. An address decoder that gives a signal to notify that it is a high-speed data transfer space access at the same time, and the output of the base address register and the address of the corresponding bit position from the address bus are input to notify from the address decoder during normal access. An address selector that selects the address bus side and supplies it as an upper address to the second storage device and selects the address on the base address register side during high-speed data transfer and supplies it as the upper address to the second storage device; and an address decoder. When there is a notification of high-speed data transfer from the second storage device to the transfer source, the read address is calculated from the base address, and only the data to be transferred is read from the address where the transfer source data is stored. Transfer to the first storage device, and if the first storage device is the transfer source, the second storage device By including a high-speed data transfer control circuit which calculates an address to be written in the memory device from the base address and transfers the data read from the first memory device, the normal access and the high-speed data transfer space are divided by the address to store two memories. In the conventional DM, a circuit for converting an address and a simple control circuit for directly writing the read data output on the data bus to the transfer destination storage device are added to one of the devices.
In the case of the A method, there is an effect that high speed transfer of one word can be performed in one read cycle of the processor without a problem of transfer time loss due to bus arbitration or hardware amount.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a function of a high speed data transfer control circuit shown in FIG.

3 is a structural diagram of an address map of the high-speed data transfer control circuit shown in FIG.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

[Explanation of symbols]

 1 processor 1a address bus 1b data bus 2 storage device 3 storage device 4 address decoder 5 base address register 6 address selector 7 high-speed data transfer control circuit 11 processor 15 offset register 16 mask gate 17 address adder 20 address map 21, 22 normal access Space 23, 24 High-speed data transfer space 70 Data transfer determination unit 71 Offset value calculation unit 72, 74 Offset address calculation unit 73 Offset value calculation unit 75 Address notification unit

Claims (3)

[Claims] 1. A processor for controlling a system including a base address and a function for outputting the address, and an address bus connected to the processor for transmitting the address.
A data bus connected to the processor for transmitting data, and a first bus connected to the address bus and the data bus
Storage device, a second storage device connected to the address bus and the data bus, and the second storage device during high-speed data transfer.
A base address register for storing a base address to be given to the storage device as a higher-order address, and one of the first and second storage devices if the result of decoding the address from the processor is a normal access space. If the result of decoding by applying a selection signal to one side is high-speed data transfer space access, the first and second
An address decoder for giving a selection signal to both of the memory devices and notifying that it is a high speed data transfer space access at the same time, and inputting the output of the base address register and the address of the corresponding bit position from the address bus. The notification from the address decoder selects the address bus side during normal access and supplies it to the second storage device as an upper address, and selects the address on the base address register side during high speed data transfer to select the second address. When an address selector is supplied to the storage device as a high-order address, and when the address decoder notifies the high-speed data transfer from the second storage device as a transfer source, the read address is calculated from the base address and transferred. Read only the data to be transferred from the address where the original data is stored. First perform transfer serial first storage device
When the second storage device is the transfer source, the write address of the second storage device is calculated from the base address and the first address is calculated.
And a high-speed data transfer control circuit for transferring the data read from the storage device. 2. A processor for outputting an offset value and an address to the processor, and an offset register for storing an offset value for adding the base register to an address on the address bus during high-speed data transfer from the processor, to the address. A mask gate that outputs the value of the offset register when the selector is disconnected from the address bus and the high-speed transfer space access is notified from the address decoder, and outputs "0" in the normal access space. The output of the mask gate and the address on the address bus are added to the value of the offset register passed through the mask gate and the address on the address bus, and the result is added to the second
2. A high-speed data transfer system according to claim 1, wherein said high-speed data transfer system is connected to an address adder supplied as an address of said memory device. 3. The normal access space of the first storage device, the normal access space of the second storage device, and the high speed of the first storage device, wherein the high-speed data transfer control circuit is mapped one-to-one with each other. An address map composed of a data transfer space and a high-speed data transfer space of the second storage device, and referring to the address map by the data from the address decoder, the first storage device to the second storage device. A data transfer determination unit that determines whether data is transferred to a device, transfer from the second storage device to the first storage device, normal data transfer, or high-speed data transfer; If it is determined that the transfer is from the device to the second storage device, the head of the data stored in the first storage device in the address map and the normal access space A first offset value calculation unit that calculates an offset value from a relative address with respect to the head of the first storage device, and a relative address portion from the offset value calculated by the first offset value calculation unit in the address map of the first storage device. A first offset address calculation unit that calculates an address in the high-speed address space by adding it to the start address of the high-speed data transfer space, and the data transfer determination unit from the second storage device to the first storage device. If it is determined that the data is transferred to the second storage device, an offset value is calculated from the relative address between the start of the data stored in the second storage device and the start of the normal access space of the second storage device in the address map. 2 offset value calculation unit and the offset value calculated by the second offset value calculation unit, A second offset address calculator that calculates an address in the high-speed address space by adding it to the start address of the high-speed data transfer space of the first storage device in the resmap; and the first and second offset addresses. 3. The high-speed data transfer system according to claim 1, further comprising an address notification unit that notifies the first storage device of the address calculated by the calculation unit.