JPH05210616A - Computer device - Google Patents

Abstract

PURPOSE:To transfer a large quantity of data without obstructing an instruction executing speed by executing a DMA transfer at the timing of an instruction fetch in an instruction cycle. CONSTITUTION:When a DMA requesting signal is outputted from an input/ output device 106, a DMA controller 105 is activated, and the bus selection signal of a high level is outputted in an instruction fetch cycle. That is, at the timing of the instruction fetch cycle, multiplexers (MUX) 201-203 select an exclusive address bus 205 from a DMA controller, a read/write signal 212 from the DMA controller, and an exclusive data bus 209 from the input/output device, respectively. Accordingly, in one instruction cycle, at the timing when a CPU does not make access absolutely to a RAM 103, that is, in an instruction fetch cycle 302, the DMA transfer is executed between the RAM 103 and the input/output device 106.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer device, and more particularly to a so-called DMA (Direct Memory Access) between a readable / writable memory device and a peripheral circuit.
ss) to a computer device for transferring data.

[0002]

2. Description of the Related Art Data transfer between a peripheral circuit and a memory by a conventional DMA method will be briefly described with reference to FIG.

In the conventional example shown in FIG. 1, a central control unit (hereinafter referred to as CPU) 101 for executing instructions to control arithmetic operations and storage devices and peripheral devices, and a read-only storage device (hereinafter referred to as ROM) for storing instructions. 102, a readable / writable storage device (hereinafter, RAM) 103 for storing data, and a DM
It is composed of a DMA controller 105 for controlling data transfer according to the A system and an input / output device 106 that requires a large amount of data transfer. Also, the address in the figure
The bus 107 is a bus through which the CPU 101 and the DMA controller 105 send addresses to the RAM 103 and the ROM 102, and the data bus exchanges commands read from the ROM 102 and data read from and written to the RAM 103 with the CPU 101 and the input / output device 106. It is a bus to do. Here, the DMA controller 105
Is activated when it receives the DMA request signal 115 from the I / O device 106, and the address bus 107 or the data bus 1 is activated.
08 is a controller that separates 08 from the CPU 101 and controls high-speed data transfer between the RAM 103 and the input / output device 106.

When DMA transfer is not performed (hereinafter referred to as non-D
MA transfer) CPU 101 has an instruction fetch cycle (see FIG. 3) for reading an instruction from ROM 102.
302) and an execution cycle (303 in FIG. 3) for accessing the RAM 103 or the ROM 102 and executing an operation according to the read instruction (301 in FIG. 3) are repeated to sequentially execute the instructions. At this time,
The DMA controller 105 sends the bus request 104 to C
When issued to PU 101, data
The bus 108 is released from the CPU 101. At the same time, the RAM 103 and the input / output device 106 start data transfer (DMA transfer) not via the CPU 101. At this time, since the CPU 101 releases the data bus 108, the execution of the instruction is actually stopped during the DMA transfer. Therefore, the substantial instruction execution speed of the CPU is reduced.

Here, although it is possible to slow down the data transfer rate by the DMA to substantially increase the instruction execution speed of the CPU, the input / output device displays a character on the television receiver (screen image display device). When it is necessary to read the RAM in synchronization with the horizontal synchronizing signal of the screen display and transfer a large amount of data like a display controller (hereinafter referred to as IDC), it cannot be delayed from the horizontal synchronizing signal. However, the DMA transfer must always be performed, and the data transfer rate by the DMA cannot be slowed to increase the instruction execution speed of the CPU.

[0006]

In the conventional data transfer by the DMA system, the C transfer is performed by the DMA transfer as described above.
As a result, the execution of PU instructions is hindered and the actual CPU instruction execution speed decreases. RAM and DM at this time
If the peripheral device that performs A transfer always needs to transfer a large amount of data at a predetermined timing, like IDC, CP
Much of the instruction execution time of U is devoted to DMA transfer, which affects the operation of other peripheral devices and CPUs that require high-speed processing.

[0007]

A computer system according to the present invention comprises a central processing unit, a read-only storage means for storing instructions, a readable / writable storage means for storing data, and an input / output means. The input / output unit and the readable / writable storage unit are connected during a period in which the central processing unit reads an instruction from the read-only storage unit.

[0008]

EXAMPLES Next, specific examples of the present invention will be described with reference to FIGS. 2 is a block diagram showing a specific operation of the computer apparatus of the present invention, and FIG. 3 is a basic bus timing chart according to the present invention. The same blocks as those in FIG. 1 are designated by the same reference numerals and detailed description thereof will be omitted.

In addition to the structure of FIG. 1 showing the conventional DMA operation, the present embodiment has a bus select signal 204 output from a DMA controller and a high level of the bus select signal 204, that is, a DMA transfer. Sometimes the dedicated address bus 205 from the DMA controller 105
When the bus select signal 204 is low level, that is, non-D
A multiplexer (hereinafter referred to as MUX) 201 that connects the bus 206 from the address bus 107 to the address bus 207 to the RAM 103 during MA transfer, and a dedicated data bus 209 from the input / output device 106 during DMA transfer similarly. , Data bus 108 during non-DMA transfers
Data bus 20 from RAM 210 to RAM 103
8 and the read / write signal 212 from the DMA controller 105 during DMA transfer,
Read / write signal 21 from CPU during non-DMA transfer
The MUX 202 outputs 1 as a read / write signal 213 to the RAM 103.

Here, one instruction cycle 301 is an instruction fetch cycle 302 and RAM, R
It consists of an execution cycle 303 for accessing the OM and performing operations. Here, in the instruction fetch cycle 302, the data bus 108 is the ROM 10
Access only 2.

When the DMA request signal 117 is at a low level (307 in FIG. 3), the DMA controller is not activated, so the bus select signal is at a low level. Therefore, MUX 201-203
During the fetch cycle 302 and the execution cycle 303, the bus 206 from the address bus 107,
Read / write signal 211 and data from CPU
Bus 210 from bus 108 is selected. Next, when the DMA request signal is output from the input / output device 106 (308 in FIG. 3), the DMA controller 105 is activated and outputs a high level bus select signal in the instruction fetch cycle 302. That is, at the timing of this instruction fetch cycle 302, the MUXs 201 to 203 respectively select the dedicated address bus 205 from the DMA controller, the read / write signal 212 from the DMA controller, and the dedicated data bus 209 from the input / output device. (3 in FIG. 3
06). This will cause the CPU to RA in one instruction cycle.
At the timing of never accessing M103, that is, at the instruction fetch cycle 302, RA
DMA transfer between the M103 and the input / output device 106 is performed. At this time, the CPU 101 is not hindering its substantial instruction execution speed.

Next, a second embodiment of the present invention will be described with reference to FIG.

In this embodiment, a dual port RAM is used instead of the RAM in the first embodiment, and the MUXs 201 to 203 in FIG. 2 do not exist. The basic operation is performed at the timing shown in FIG.

Here, one instruction cycle 301 is an instruction fetch cycle 302 and RAM, R
It consists of an execution cycle 303 for accessing the OM and performing operations. Here, in the instruction fetch cycle 302, the data bus 108 is the ROM 10
Access only 2.

When the DMA request signal 117 is at a high level (308 in FIG. 3), that is, when the DMA controller 105 is active, the DMA controller 105 outputs a high level bus select signal 204 in the instruction fetch cycle 302. At this timing, the CPU 101 absolutely operates the dual port RAM 4
01 is not accessed, the dual port RAM 401 receives the read / write signal 212 from the DMA controller 105, accesses the DMA controller and the input / output device through the dedicated address bus 402 and the dedicated data bus, and performs the DMA transfer. To do. C for non-DMA transfer
It receives a read / write signal from the PU and performs a normal operation via the bus 403 and the bus 405. DM as above
Since the timing of the A operation and the timing of the CPU 101 accessing the dual port RAM 401 are completely time-shared in one instruction cycle 301, RAM contention does not occur.

[0016]

As described above, in the computer device according to the present invention, by performing the DMA transfer at the instruction fetch timing in the instruction cycle, the instruction execution time of the CPU becomes long during the DMA transfer, It is possible to solve the problem that the contention of the RAM occurs when the dual port RAM is used as the RAM, and a large amount of data is transferred between the RAM and the input / output device without impeding the substantial instruction execution speed of the CPU. The effect is that transfer is possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing a conventional technique.

FIG. 2 is a block diagram showing an embodiment of the present invention.

FIG. 3 is a timing chart in the present invention.

FIG. 4 shows a dual port RAM in FIG.
It is a block diagram when it replaces with.

Claims (1)

[Claims] 1. A computer device having a central processing unit, a read-only storage unit for storing instructions, a readable / writable storage unit for storing data, and an input / output unit, wherein the central processing unit is from the read-only storage unit. A computer device, wherein the input / output unit and the readable / writable storage unit are connected during a period for reading out an instruction.