JPH1063565A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processor capable of eliminating a waiting time for delay in a period until the setting of input data to a first storage means through a synchronizing circuit is reflected to a device. SOLUTION: When a DEVSEL control part 12 recognized access from CPU 1 to be a right access to an internal GR (general purpose) register 17 related with the control of DEVSEL (device select) # signal, address and data are written to an FIFO buffer 14 for access to the actual GR register 17 and the right data is also stored in a shadow register 13 near a DEVSEL control part 12 at the same time. This shadow register 13 is used for judging whether to activate the DEVSEL # signal by the control part 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data processing device.

[0002]

2. Description of the Related Art In order to clarify the background of the invention, first, a related matter, PCI (Peripheral Comp) is described.
one-on-one interconnect bus system and VGA (Video Graphics Array)
y) The device will be described.

FIG. 3 is a schematic configuration diagram of a PCI bus system. The PCI bus system includes a CPU 1, a PCI bus 2, a device 9, a device 10, and so on. Items related to the present invention among the features of the PCI bus are described below.

[0004] 1. The devices 9, 10,... Connected to the PCI bus 2 share signal lines for addresses, data, and the like.

[0005] 2. Each of the devices 9, 10,... Is assigned a unique memory and I / O space.

[0006] 3. In the case of accessing the memory and the I / O space, the CPU 1 selects the devices 9, 10,.

[0007] 4. Each of the devices 9, 10,... Determines from the address whether or not the device is an access to its own device.
The L (DEVICE SELECT) signal 8 must be activated.

In the case of a VGA device, the accessible space can be switched by the internal register. FIG. 4 shows an example of a space accessible by the register, and FIG. 5 is a diagram for explaining the accessible space of FIG.

In FIG. 5, a shaded portion is an accessible space. VGA GR (General,
When the register is (00) ₂ , the accessible space is A0000h to BFFFFh. When the internal register is (01) ₂ , the access range is A0000h to BFFFFh.
AFFFFh is set, and B0000h to BFFFFh cannot be accessed. In the case of (10) ₂ , B
0000h to B7FFFh, (11) B80 for ₂
Only 00h to BFFFFh are accessible spaces,
Other addresses cannot be accessed.

In the case of a VGA device compatible with the PCI bus,
Since the access space changes depending on the GR register of the VGA, it is necessary to change the control of the DEVSEL signal 8.
In FIG. 5, the shaded portion is accessible,
The device must activate the DEVSEL signal 8 but must not activate it because other addresses are inaccessible. in this case,
Since the accessible space is switched depending on the value of the GR register, it is necessary to refer to the value of the GR register for controlling the DEVSEL signal 8.

FIG. 6 is a schematic configuration diagram of a VGA device system compatible with a PCI bus, which is a conventional technique. PC
The system of the VGA device corresponding to the I bus is CPU1, P
CI bus 2 and device 10
Is a bus interface 11, a DEVSEL control unit 12 for controlling a DEVSEL signal, and a FIFO (FirstI
n First Out, first-come-first-served processing method) buffer 1
4, internal bus 15, memory 16, GR register A17,
...

The operation of this system will be described. C
In response to an access from the PU1, the device 10 receives the address via the bus interface 11 and determines whether or not the device is accessed by the DEVSEL control unit 12, and if so, activates the DEVSEL signal 8 to respond to the access. C to do
Notify PUl. In the DEVSEL control unit 12, D
The control of the EVSEL signal 8 refers to the DEVSEL control signal 18 coming from the GR register 17.

In the case of write access, the address, data, and the like received from the CPU 1 are stored in the FIFO buffer 14, and the TRDY # signal 7 is sent to the CPU 1 at that time.
Informs the end of access. In this way, the memory 16, GR, which is actually the target of access,
A method of terminating a write cycle before writing to the register 17 or the like is that when a device with a slow access such as a memory is allocated, access to the memory 16 or the GR register 17 which is the target of the access is actually waited. CPU1 can issue the next command without
This is effective for reducing the load on the CPU1. Even when instructions from the CPU 1 are stored in the plurality of FIFO buffers 14, the order between the instructions does not change and the next instruction is executed after the previous instruction is executed. Therefore, no inconsistency is caused by the FIFO buffer 14. .

In the case of a read cycle, device 10
Since the cycle ends when the read data is returned to the PUl, the address received from the CPUl passes through the FIFO buffer 14 and the actual target memory 16,
The next command is not issued until the data is read from the GR register 17 and the like and passed to the CPU 1. F
Since this read instruction is performed after processing of all unexecuted instructions in the FIFO buffer 14 is completed, no unexecuted instructions are stored in the FIFO buffer 14 after the read cycle.

The above-mentioned GR register 1 of the VGA device
An example of an access related to an operation in which the control of the DEVSEL signal 8 is changed by 7 will be described with reference to FIG. FIG. 7 is a timing diagram of a system of a VGA device compatible with a PCI bus according to the related art.

An attempt is made to set (10) ₂ from T _{2 to} T ₅ while the value of the GR register 17 is (01) ₂ . T ₂
Receives the address 100 of the GR register 17 at T ₃
Acknowledgment by DEVSEL. Receives write data 101 at T _4, writes the write data 101 received by the address 100 and T ₄ received in T ₂ to the FIFO buffer l4 in pairs in the FIFO buffer l4 TR
Completion of write cycle by DY # signal 7
Inform Since the write cycle for setting (10) ₂ in the GR register 17 has already been completed, the CPU 1 determines that the access to the address B0000h is possible. However, in until T ₂₁ of the write data (10) ₂ to GR register 17 is reflected from this point, DEVSEL control unit 12 to operate by referring to the previous value (01) ₂ of GR register 17 , Address B0
When access to 000h is performed, the DEVSEL signal 8 is not activated and malfunctions.

Therefore, it is necessary to wait for access to B0000h until the setting of the GR register 17 is completed. As an example of the wait means, an invalid read cycle is issued. The time until the value is actually set in the GR register 17 depends on the number of unexecuted commands stored in the FIFO buffer 14, but as described above, after the end of the read cycle,
Since all the commands in the FO buffer 14 have been completed, it is guaranteed that the setting of the GR register 17 has been completed. By issuing the invalid read cycle, a malfunction can be prevented, but access to B0000h is delayed by one read cycle.

[0018]

The above-mentioned prior art has the following problems.

In the system described above, after a write access to a register that affects the control of the DEVSEL, the CPU must wait until the access is reflected in the actual register.
Even if the load is reduced, the processing speed is reduced by the weight.

In view of the above-mentioned problems of the prior art, it is an object of the present invention to provide a device for delaying until the setting of the input data to the first storage means via the synchronization circuit is reflected on the device. An object of the present invention is to provide a data processing device capable of eliminating a wait time.

[0021]

According to the present invention, there is provided a data processing apparatus for storing input data in a first storage means via a synchronization circuit. In order to store the same value as the first storage means, if the value to be set in the first storage means is not immediately written and a time delay occurs, The input data is also stored in the second storage means, and the input data of the second storage means is output in response to a reference request to the first storage means.

Therefore, until the setting of the input data to the first storage means via the synchronization circuit is reflected on the apparatus, the setting value of the input data of the second storage means held separately is used. Wait time for delay can be eliminated.

Further, the data processing device is a system in which the accessible range is switched according to the value of an internal register, the synchronization circuit is a FIFO buffer, the first storage means is a register, and the second storage means is Since this is a shadow register and the input data is stored in the register via the FIFO buffer, if the value to be set in the register is not immediately written and a time delay occurs, it is necessary to immediately hold the same value as the register. For the purpose, the input data may be stored in the shadow register, and the input data of the shadow register may be output in response to a reference request to the register.

Therefore, the wait time until the setting can be eliminated by referring to the shadow register.

[0025]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a schematic configuration diagram of a system of a VGA device compatible with a PCI bus according to an embodiment of the present invention. In the system of FIG. 1, in addition to the system configuration of the VGA device corresponding to the PCI bus of the related art of FIG. 6, a DEVSEL signal 8 such as a GR register 17 is provided.
The bus interface 11 has a shadow register 13 for holding the same value as that of the register referred to by the control.

In response to the access from the CPU 1 to the GR register 17, the address received by the bus interface 11 is decoded, and when it is determined that the write access to the GR register 17 is made, the shadow register 13 holds the same value as the write data. I do. This shadow register 13
Is written without going through the FIFO buffer 14, the set value is reflected when the CPU 1 is notified of the end of the write cycle by the TRDY # signal 7.

The DEVSEL control section 12 refers to the shadow register 13 for controlling the DEVSEL signal 8. Since the shadow register 13 already holds the set value in the GR register 17 at the end of the write access, there is no need to wait for the time from when the GR register 17 is set to when it is actually set in the GR register 17. The bus interface 11 provides a FIFO buffer 14 for accesses other than writing to the GR register 17 as in FIG.
Access the actual target through. G
For the write access to the R register 17, only the write data is stored in the shadow register 13, and the subsequent operation is the same as in the case of FIG. 6, and the write access to the GR register 17 is performed through the FIFO buffer 14. DE
DEVS from GR register 17 in VSEL control unit 12
The EL control signal 18 is not referred to.

FIG. 2 is a timing chart of the system of the VGA device corresponding to the PCI bus according to the embodiment of the present invention.

The access timing will be described with reference to FIG. An attempt is made to set (10) ₂ from T _{2 to} T ₅ from the state where the value of the GR register 17 is (01) ₂ . It receives an address 100 of GR register 17 at T _2, the acknowledgment by DEVSEL at T _3. It receives write data 101 at T _4, address 100 received in T ₂
Then, the completion of the write cycle is notified to the CPU 1 by the TRDY # signal 7 by writing the data into the FIFO buffer 14. The DEVSEL controller 12 recognizes that the address 100 received by the T ₂ is a GR register 17 f write access, and stores the write data 101 of the GR register 17 f in shadow register 13 at T _4.
Since the write cycle for setting (10) ₂ in the GR register 17 has already been completed, the CPU
It is determined that access to 0000h is possible.

[0030] In the period from the time point to T ₂₁ to write data (10) ₂ to GR register 17 is reflected, the value of GR register 17 is (01) ₂ before the setting, DEV
Since SEL control unit 12 for controlling the DEVSEL signal 8 (10) ₂ with reference to the GR register 17 rather than the shadow register 13 for B0000h access line of T ₇ through T _10, without having to put the wait cycle can be not malfunction activating the DEVSEL signal 8 is also T _8. Internal operation for access T ₂ through T _5, the data 10 written in the FIFO buffer l4 with T ₄
1 is written in the GR register 17 through T ₂₁ an internal bus 15. This is similar to the system shown in FIG.

In the system using the shadow register 13 as described above, the next command can be issued without being conscious of whether or not the write data has been written in the GR register 17 which is actually the target of access. .

[0032]

As described above, in the system of the present invention, it is not necessary to be aware of the time delay from when the CPU terminates the write access to when the write data is actually set, thereby increasing the processing speed. There is an effect that can be.

In FIG. 7 of the prior art, an invalid read cycle for generating a wait after the setting of the GR register 17 is issued, but in FIG. 2 using the present invention, the wait after the setting of the GR register 17 is performed. The next command can be issued without using the present invention, and the use of the present invention speeds up access by one read cycle.

That is, the internal GR register 1 in FIG.
When performing read access to the memory 7 and the memory 16,
3 clocks before writing to the I / O buffer 14, FI
It takes five clock at least until written from FO buffer l4 to GR register 17 and a memory 16, a write access T ₂ through T ₅ in FIG. 7, the read access _{T 7 ~T 25, T 27 ~T} 30 lights The access takes 4 + 1 + 8 + 1 + 4 = 18 clocks, taking into account that one clock is inserted between accesses. On the other hand, in the system of the present invention, as shown in FIG. 2, 4 + 1 + 4 = 9 clocks, and the speed is improved by 50% for such access.

[Brief description of the drawings]

FIG. 1 is a VGA compatible with a PCI bus according to an embodiment of the present invention.
It is a schematic block diagram of the system of a device.

FIG. 2 is a VGA compatible with a PCI bus according to the embodiment of the present invention.
FIG. 2 is a timing diagram of the device system.

FIG. 3 is a schematic configuration diagram of a PCI bus system.

FIG. 4 is an example of a space accessible by a register;

FIG. 5 is a diagram for explaining an accessible space in FIG. 4;

FIG. 6 is a schematic configuration diagram of a system of a VGA device compatible with a PCI bus, which is a conventional technique.

FIG. 7 is a timing diagram of a system of a VGA device compatible with a PCI bus, which is a conventional technique.

[Explanation of symbols]

 Reference Signs List 1 CPU 2 PCI bus 3 FRAME # signal 4 AD signal 5 C / BE # signal 6 IRDY # signal 7 TRDY # signal 8 DEVSEL # signal 9, 10 device 11 Bus interface 12 DEVSEL control unit 13 Shadow register 14 FIFO buffer 15 Internal bus 16 Memory 17 GR register A 18 DEVSEL control signal

Claims (2)

[Claims] 1. A data processing device for storing input data in a first storage means via a synchronization circuit, wherein the input data is stored in the first storage means via the synchronization circuit. When a value to be set in the first storage unit is not immediately written and a time delay occurs, the input data is stored in the second storage unit for the purpose of immediately holding the same value as the first storage unit. A data processing device, wherein the data is also stored in a storage unit, and the input data of the second storage unit is output in response to a reference request to the first storage unit. 2. The data processing device is a system in which an accessible range is switched according to a value of a register included therein; the synchronization circuit is a FIFO buffer; the first storage unit is the register; The second storage means is a shadow register. Since input data is stored in the register via the FIFO buffer, when a value to be set in the register is not immediately written and a time delay occurs, the same as the register is used. The input data is also stored in a shadow register for the purpose of immediately holding the value of the shadow register, and the input data of the shadow register is output in response to a reference request to the register. Data processing equipment.