JPH0261745A - Read transfer control system for dmac - Google Patents

Abstract

PURPOSE:To shorten the waiting time of an I/O (input/output) part to improve the data transfer performance by preliminarily accessing a memory to hold read data in a buffer and transferring read data from the buffer to the I/O part in accordance with the transfer request of the I/O part. CONSTITUTION:An advance read indicating part of a DMAC (direct memory access controller) instructs a memory bus control part 23b to perform the read access. This control part 23b outputs a read buffer enable signal RBFE to a read buffer 22a to set data on a memory bus 5b to the read buffer 22a through a receiver R1. A DMA bus control part 23c receives the data transfer request of an I/O part 4 and outputs a DMA data enable signal DDEN to a driver D2 to output read data in the read buffer 22a onto a DMA bus 5c. The I/O part 4 receives data from the DMA bus 5c and processes reception data.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figure 4) Means for solving the problem to be solved by the invention (Figure 1) Working example (a) 1 Explanation of the configuration of the embodiment (Figure 2) (b)
Explanation of operation of one embodiment (Fig. 3) (C) Explanation of other embodiments Effects of the invention [Summary] DMAC that controls data transfer between memory section and I/O section
Regarding the data transfer control method during read transfer in /O section and memory section are connected via a hash, and in response to a transfer request from the I/O section, the memory section is accessed for the set number of bytes from the set address, and the I/O section is
A DMAC that transfers data to the memory section is provided with a buffer that stores read data from the memory section, and a advance read instruction section that instructs to read data from the memory section in advance in the read transfer mode. Before the I/O section transfer request, data is read in advance from the memory section to the buffer according to the instruction from the advance read instruction section, and the data is read from the memory section to the buffer in advance.
In response to a transfer request from part O, the data in the buffer is transferred to part I.
/Transfer to department O.

[Industrial application field]

The present invention relates to a data transfer control method during read transfer in a DMAC that controls data transfer between a memory section and an I/O section.

In a computer system, there is a method of transferring data between the I10 (human output) section and the memory section using a DMAC (Direct Memory Access Controller) dedicated to data transfer without intervening a processor.

In data transfer using such a DMAC, as the speed of the I/O section increases, there is a demand for faster data transfer between the memory section and the I/O section.

For this reason, attempts have been made to speed up the memory bus, but since the performance is determined by the access cycle of the memory element, it is desired to devise a DMAC data transfer control system in order to achieve even higher speeds.

[Conventional technology]

FIG. 4 is an explanatory diagram of the prior art.

In FIG. 4(A), bus 5 connects processor l to
A DMAC 2, a memory section 3, and an I/O section 4 are connected.

In the conventional DMAC2 data transfer control, Fig. 4(B)
As shown in the figure, in the read transfer mode, after setting the start address and number of transfer bytes from the processor 1 and receiving a DMA start instruction, a data transfer request is received from the I/O section 4, and the access right to the bus 5 is granted. A sea fence was used in which the data was acquired, read access was made to the memory section 3, and the read data was transferred to the I/O section 4.

Further, in the write transfer mode, after receiving a pig transfer request from the I/O section 4 and responding, write access to the memory section 2 is performed.

[Problem to be solved by the invention]

Incidentally, since the bus 5 is shared not only with the DMAC 2 but also with other control units and the like, it may take time to access the memory after obtaining access rights to the bus 5.

For this reason, in the prior art, in read transfer mode,
As shown in FIG. 4(B), after the transfer request from the I/O unit 4,
Since the DMAC 2 obtains the right to access the bus and accesses the memory to obtain read data, the I/O unit 4 is forced to wait for a time T after the transfer request.

This waiting time is not a problem in the write transfer mode because memory access is performed after the I/O section 4 is separated, and in the read transfer mode, the data transfer performance between the I/O section 4 and the memory section 3 is greatly improved. There was a problem in that it caused a decrease in performance.

Therefore, an object of the present invention is to provide a DMAC read transfer control method that can shorten the waiting time of the I/O section and improve data transfer performance.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle of the present invention.

As shown in FIG. 1, the present invention has an operation control section 20 that updates addresses and byte counts, and is connected to an I/O section 4 and a memory section 3 via a bus 5. In response to a transfer request, a buffer 22 stores read data from the memory section 3 in the DMAC that accesses the memory section 3 for a set number of bytes from a set address and transfers data to the T10 section 4. and a advance read instruction section 21 that instructs to read data from the memory section 3 in advance in the read transfer mode, and the I/O section 4
Before the transfer request, data is read from the memory section 3 to the buffer 22 in accordance with the instruction from the advance read instruction section 21, and in response to the transfer request from the I/O section 4, the data in the buffer 22 is read. is transferred to the I/O unit 4.

[Effect]

In the present invention, the memory is accessed in advance, read data is held in the buffer 22, and the read data is transferred from the buffer 22 to the I/O section 4 in response to a transfer request from the 170 section 4.

Therefore, when a data transfer request is made from the I/O section 4, data can be transferred to the I/O section 4 in response to the request immediately.

Therefore, bus access right acquisition and memory access are as follows:
Since the data transfer request is completed before the data transfer request, the I/O section 4 can immediately change the data without waiting for the access right to be acquired.

This means that the DMAC 2 does not access the memory dependently on the data transfer request of the I/O unit 4, but accesses the memory independently, and the data transfer request is processed as a data request on the buffer 22 in the MAC2. Operate.

This memory access of the DMAC 2 can be performed at the start before a transfer request and during the data processing time of the I/O unit 4, so the I/O unit 4 is not kept waiting at all.

〔Example〕

(a) Description of the configuration of one embodiment FIG. 2 is a block diagram of an embodiment of the present invention.

In the figure, the same parts as shown in Figures 1 and 4 are:
Indicated by the same symbol.

The bus 5 includes a system bus 5a, a memory bus 5b, and a D
The system bus 5a connects the processor 1, the I/O unit 4, the DMAC 2, and a control unit 6 such as a disk controller, and the memory bus 5b connects the DMAC 2 and the memory unit 3. and the control unit 6,
The DMA bus 5C connects the DMAC 2 and the I/O section 4.

20 is the aforementioned operation (channel) control unit, which includes a start/stop register 200 that holds the start state and stop state, enables DMA transfer in the start state and disables DMA transfer in the stop state, and read transfer. mode (data transfer from memory section 3 to I/O section 4),
It has a mode register 201 that instructs a write transfer mode (data transfer from the I/O section 4 to the memory section 3).

Furthermore, the channel control unit 20 includes a multiplexer 204.
The amount of data to be transferred is set via the subtracter 203 for each data transfer, and '-IJ is subtracted by the subtracter 203. When OJ is reached, the DMA transfer is finished and the start/stop register 2
A memory address is set via a data register 202 with 00 as a stop state and a multiplexer 207,
The address register 205 is incremented by "+1" by an adder 206 every time one data transfer is performed.

Reference numeral 21 denotes the above-mentioned advance read instruction section, and when the channel control section 20 starts in the read transfer mode, it issues a read access instruction to the memory bus control section, which will be described later, and then performs data transfer by the DMA control section, which will be described later. End (1
DMA read access instruction at the end of each data transfer)
This is done until the transfer is completed.

22a is a read buffer, which temporarily holds read data from the memory section 3; and 22b is a write buffer, which temporarily holds write data to the memory section 3.

23a is a system bus control unit, which controls DMA by read and write access from the upper level (processor 1, etc.).
23b is a memory bus control unit that controls reading and writing to registers 200, 201, 202, 205, etc. inside C, and controls acquiring access to the memory bus 5b and acquiring access to the memory unit 3 via the memory bus 5b. The control unit 23c is a DMA bus control unit, which controls data transfer with the I/O unit 4 via the DMA bus 5C.

24 is an interrupt generation unit, and DM of the channel control unit 20
R1 and R2 are receivers that notify the host (processor 1) of the completion of A transfer as an interrupt through the system bus 5a, and receive read data from the memory unit 3, I/O, etc.
Receives write data from O unit 4 and writes it to read buffer 2
2a, it is output to the write buffer 22b.

Dl, D2, and D3 are each drivers, and the driver DI
outputs the write data of the write buffer 22b to the memory bus 5b in response to the memrist enable signal MDEN of the memory bus control unit 23b, and the driver D2 outputs the write data of the write buffer 22b to the memory bus 5b.
DMA data enable signal DD of A bus control unit 23C
In response to EN, the driver D3 outputs the read data of the read buffer 22a to the DMA bus 5c, and in response to the address enable signal ADE of the memory bus control unit 23b, the driver D3 outputs the memory address of the address register 205 to the memory bus 5b. It is something.

In this embodiment, the bus 5 is composed of three buses: a system bus 5a, a memory bus 5b, and a DMA bus 5C, which reduces the load on the bus and enables high-speed access.

(b) Description of operation of one embodiment FIG. 3 is a time chart diagram of one embodiment of the present invention.

Here, the priority order of access rights on the memory bus 5b is as follows:
It is assumed that the control unit 6 is higher.

(2) At the start of DMA, the processor l inputs the read transfer mode, transfer data!, to each of the mode register 201, data register 202, and address register 205 of the channel control unit 20 of the DMAC 2 via the system bus 5a. (number of bytes) and set the memory address.

Thereafter, the processor 1 sets a start state in the start/stop register 200 of the channel control unit 20, and the DMAC 2 enters the start state.

With this start state and read transfer mode, the advance read instruction section 21 is activated, and the advance read instruction section 21
A read access instruction is given to the memory bus control unit 23b.

(2) The memory bus system JB section 23b turns on the access request α in order to obtain the right to access the memory bus 5b.

And the system? If the access request β of the first part 6 is off and the memory bus 5b is not busy, the access response is turned on and the access right to the memory bus 5b is acquired.

(2) As a result, the memory bus control section 23b outputs the address enable signal ADE to the driver D3, and outputs the memory address (m) of the address register 205 to the memory bus 5b.

As a result, the memory unit 3 outputs the data (RDI) of the memory address (m) to the memory bus 5b.
The memory control unit 23b receives a read buffer enable signal R.
Output BFE to read buffer 22a, memory bus 5b
The above data (RDl) is set in the read buffer 22a via the receiver R1.

■ By processor l, I
When the /O section 4 is instructed to start I10, the DMA of the I/O section 4 is started.

The 170 unit 4 outputs a data transfer request γ to the DMAC 2 from the DMA bus 5c to issue a data transfer request.

- The DMA bus control unit 23c receives the data transfer request T, and since valid data (RDI) is set in the read buffer 22a, it immediately outputs a data transfer response to the I/O unit 4 and outputs a DMA data enable signal DDEN. is output to the driver D2, and read data (RDI) of the read buffer 22a is output to the DMA bus 5c.

The I/O unit 4 receives data from the DMA bus 5C and processes the received data.

■ This data transfer response causes the channel control unit 20
sets the memory address of the address register 205 to (m+
1), the contents of the data register 202 are updated by "-1".

At the same time, the advance read instruction section 21 issues a read access instruction to the memory bus control section 23b in response to the pig transfer response.

(2) While the I/O section 4 is processing the received data (RDI), the sequence (2) to (2) is repeated.

At this time, while the control unit 6 acquires the access right to the memory bus 5b and uses the memory unit 3, the memory bus control unit 23b waits for this, acquires the access right, and accesses the memory.

(2) In this way, the above sequence is repeated, and when the content of the data register 202 becomes "0", the DMA transfer ends and the start/stop register 200 enters the stop state.

As a result, an interrupt is generated from the interrupt generating section 24 in the processor 1, and the DMA transfer sequence ends.

When the 170 unit 4 also receives the final data, it stops DMA.

In this way, when the read transfer mode starts, the advance read instruction section 21 issues a read access instruction to the memory bus control section 2, and the memory bus control section 2 uses the access right of the memory bus 5b to read the data. The read buffer 22a is accessed and held in the read buffer 22a.

Then, when there is a data transfer request from the I/O section 4, the D
The MA bus control unit 23c immediately responds to the request, transfers the data in the read buffer 22a, and completes one data transfer.

The data transfer response is sent to the advance read instruction unit 2.
In response to this, the advance read instruction unit 21 issues a read access instruction to the memory bus control unit 23b, and thereafter repeats the above-described operations until the DMA transfer is completed.

Therefore, in the read transfer mode, data is read from the memory section 3 in advance before a data transfer request from the I/O section 4 is made, so that when a data transfer request is made from the I/O section 4, the data is immediately read. Can respond to data transfer.

(C) Description of other embodiments In the above-described embodiments, the bus 5 is composed of three buses, but the bus 5 can also be composed of one or two buses.

Although the present invention has been described above using examples, the present invention can be modified in various ways according to the gist of the present invention, and these are not excluded from the present invention.

〔Effect of the invention〕

As explained above, according to the present invention, for DMA transfer in read transfer mode, data is read from the memory section in advance before a pig transfer request from the I/O section.
This has the effect of being able to immediately respond to data transfer requests from the O unit, speeding up DMA transfer, and reducing I/O
There is no waiting time for the I/O section, which contributes to speeding up the I/O section and improves the performance of the computer system.

[Brief explanation of the drawing]

FIG. 1 is a principle diagram of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a time chart diagram of an embodiment of the present invention, and FIG. 4 is an explanatory diagram of the prior art. In the figure, ■-processor, 2-DMAC. 3-Memory section, 4-I/O section, 5-Bus, 20--Operation control section, 21-Preliminary read instruction section, 22-Buffer.

Claims (1)

[Claims] (1) It has an operation control unit (20) that updates addresses and byte counts, and has an I/O unit (4) and a memory unit (3).
) is connected to the I/O unit (4) via a bus (5), and in response to a transfer request from the I/O unit (4), the memory unit (3) is accessed by the set number of bytes from the set address, and the I/O Part (4
), the DMAC includes a buffer (22) that stores read data from the memory section (3), and a preceding buffer that instructs in advance to read data from the memory section (3) in the read transfer mode. Lead instruction section (21)
and read data in advance from the memory section (3) to the buffer (22) according to instructions from the advance read instruction section (21) before the transfer request from the I/O section (4); In response to a transfer request from the I/O unit (4), the buffer (
22) is transferred to the I/O unit (4).