JPH0516452A - Printer - Google Patents

Abstract

PURPOSE:To constitute a printer so that a bit map memory region is cleared within a short time. CONSTITUTION:The image data developed on the bit map memory of a DRAM 23 is successively outputted to a shift register 22 in the image data unit of a specified region by an address counter 21 and transmitted to an engine from the shift register 22. At each time when the image data of the specified region is outputted to the shift register 22, the data of all zero from a zero gate 25 is written in the region to clear the bit map memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printer. More specifically, the present invention relates to a printer characterized by memory control at the time of DMA transfer of image data to an engine.

[0002]

2. Description of the Related Art In a laser printer or the like, transfer of image data expanded in a bit map memory to an engine is performed by a DMA controller (Direct Memory Access Controller).
roller, hereinafter referred to as "DMA") or CPU (Central Pr
Ocessing Unit). The task of transferring this image data to the engine is simply the task of reading the data from the memory and sending it to the engine (specifically, writing to the shift register). For efficiency, it is not necessary for the CPU to perform such a simple operation. Therefore, conventionally, it is general to perform the DMA transfer using the DMA that operates independently of the CPU.

At the time of DMA transfer, only image data is sent to the engine, and nothing else is done to the memory. Therefore, even after the image data is transferred from the bitmap memory to the engine, the image data remains in the bitmap memory.

Here, the bit map memory means a memory in which one virtual page or a part thereof is formed in a memory area in which image information is recorded in which one bit corresponds to one dot. The engine means a mechanical portion that forms an image using the video data output from the shift register.

As described above, since the image data remains in the bitmap memory even after the image data is transferred from the bitmap memory to the engine, when the new page is newly created, the bit data is first transmitted. It is necessary to clear the map memory. Conventionally, this clear is performed by software and a CPU that performs clear control according to the software.

[0006]

However, the bit map memory area to be cleared is quite large. For example, if the image data written in the bitmap memory is A
Assuming image data for one page of a 4-size original,
The memory area is about 1 Mbyte. Therefore, there is a problem that it takes a very long time to clear this wide memory area, and the processing capability (performance) of the entire printer is lowered.

Therefore, in order to solve such a problem,
An object of the present invention is to provide a printer that can clear a bitmap memory area in a short time.

[0008]

In order to achieve the above-mentioned object, the printer of the present invention is arranged such that the image data expanded in the bit map memory is sequentially arranged from the bit map memory in the unit of image data of the area specified by the address counter. In the printer that performs DMA transfer to the engine after the output, a clearing unit that clears the specified area each time the image data of the specified area is output is provided.

The clearing means may be configured to perform clearing by writing predetermined data, for example, 0 (zero) in the specified area.

[0010]

According to this structure, the address counter keeps the same value until the address counter counts up to the address for specifying the next area after the image data of the specified area is output. Therefore, for example, by writing zero to the same area using the address counter value before counting up, it is not necessary for the CPU to clear it after the transfer of all data is completed.

[0011]

Embodiments (laser printers) of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the main part of this embodiment, and FIG. 2 is a diagram showing the system configuration including it.

As shown in FIG. 2, this embodiment mainly
CPU1 for controlling each unit, DMA for DMA transfer
2, a RAM 3 and a ROM 4 as a memory, a panel (PANEL) 5 used for operations, and an engine interface (ENGINE I / F) 6.

Further, in relation to FIG.
The RAM 23 and the like are included, the DMA 2 includes an address counter 21 and the like, and the engine interface 6 includes a shift register 22 and the like. Furthermore,
The zero gate 25 shown in FIG. 1 is added to the configuration of FIG. The DMA2 exists between the DRAM 23, which constitutes a bitmap memory, and the engine for control purposes, and directly transfers data.

Next, DMA transfer of image data to the engine will be described with reference to FIG. (1) First, the bus right of the CPU 1 is obtained. Normally, the data bus and address bus are dominated by the CPU 1. Therefore, by sending a signal from the DMA 2 to transfer, the CPU 1 is given up control of the data bus and the like, and the bus right is obtained.

(2) The image data in the bit map memory area indicated by the address counter 21 is read. The address counter 21 is connected to the address bus and
When the address counter 21 specifies the bit map memory area of the AM 23, a signal (/ DRAMSEL) indicating that the DRAM 23 is selected is sent to the address decoder 24.
Sent to the DRAM 23.

(3) The image data transferred from the DRAM 23 to the data bus is transferred to the shift register 22 and stored. At this time, the DMA 2 sequentially transfers the image data to the shift register 22 at an appropriate timing. When the image data transferred from the bitmap memory via the data bus is written in the shift register 22, a signal requesting video data (VIDEO), that is, a video clock (VIDEO CLOCK) is sent from the engine in pulses. come. When one pulse is input, 1 bit is output as a video signal. Since this embodiment is a laser printer, the value of the laser that outputs one bit at a time is serial. Therefore, in order to put parallel data in the shift register 22 and output it serially, output is performed at the timing required by the engine.

(4) A signal (/ ZEROGATE) is input from the address decoder 24 to the zero gate 25, and D
When a write signal is input to the RAM 23, the DRAM 23 reads all-zero data (D0 to D7). (5) Since the address counter 21 still indicates the area where the image data has been read out, zero is written in the original bitmap memory area using the address value. (6) Return the bus right to CPU1.

The above operations (1) to (6) are repeated to transfer all the image data. Every time the image data is transferred to the shift register 22 in (3), the image data is cleared in (5), so it is not necessary to clear it after transferring all the image data.

In repeating the DMA transfer of the area specified by the address counter 21 ((1) to (6)), the bus right is once returned to the CPU in (6). This is during the time to take the timing required by the engine in (3) above,
This is for operating the CPU 1. For example, in terms of 8-bit units, when 8-bit image data written in the shift register 22 is output to the engine bit by bit in accordance with a clock, it is necessary to take timing so that the image is not interrupted. When the unoutputted image data of the shift register 22 is lost, the image is interrupted there, so that the bus right is acquired at a timing that does not interrupt the image. For example, when 4 bits are output, the DMA2 is activated again by (1) and the shift register 2
The operation of writing to 2 is repeated.

[0020]

As described above, according to the present invention, the image data expanded in the bit map memory is sequentially output from the bit map memory in the unit of image data in the area specified by the address counter, and then output to the engine. D
A printer that performs MA transfer is provided with a clear unit that clears the specified area each time image data of the specified area is output, so that the bitmap memory area can be cleared in a short time. It is possible to realize a printer that can. As a result, the processing capacity of the printer can be significantly improved. Also, since software for clearing the memory area is not required,
There is also an effect that the size of the program can be reduced as a whole.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a system according to an embodiment of the present invention.

[Explanation of symbols]

1 ... CPU 2 ... DMA 3 ... RAM 4 ... ROM 5 ... Panel (PANEL) 6 ... Engine interface (ENGINE I /
F) 21 ... Address counter 22 ... Shift register 23 ... DRAM 24 ... Address decoder 25 ... Zero gate

Claims (3)

[Claims] 1. A printer that performs DMA transfer to an engine after sequentially outputting image data expanded in a bit map memory in image data units of an area specified by an address counter from the bit map memory, A printer provided with clearing means for clearing the image area every time image data is output. 2. The printer according to claim 1, wherein the clearing means performs the clearing by writing predetermined data in the specified area. 3. The printer according to claim 2, wherein the predetermined data is zero.