JP3031074B2 - Image processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus,
In particular, the present invention relates to an image processing device that writes image data to a memory and processes the image data.

[0002]

2. Description of the Related Art Conventional image processing apparatuses are widely used in companies that issue publications such as newspaper companies and printing companies, as well as general facsimile machines. Among them, newspaper companies output image data for one page received from a line as it is for one page. That is, one page of image data is stored in the memory of the image processing apparatus, and the image data is read from the image memory in units of one line of one page.

[0003]

The conventional image processing apparatus described above has a drawback that it is not possible to output two-page spread image data (one page) like a newspaper. Further, for example, in the case of transmitting an A2-size image such as a newspaper and recording one page of the entire spread, that is, the A1 size, the image data is also recorded at the boundary between the first and second pages of the A2 size. There is a drawback that you can not.

[0004]

According to the present invention, there is provided an image processing apparatus comprising: an image memory for storing image data; a write address control circuit for setting and controlling a write address of the image memory; and a read address of the image memory. setting a read address control circuit for controlling the interrupt generation circuit writing of one line is interrupt notification to the CPU that it has finished, and a CPU for controlling the operation of the various parts, usually two pages to be written to said image memory Minute Day
1 page corresponding to the data between the 1st and 2nd pages
The amount of data for
It is characterized by outputting a two-page spread image.

In the above-mentioned image memory, a normal 2
In addition to the page data, a data amount for one page corresponding to the data between the first and second pages is stored, and a continuous one-page spread image is output at the time of recording and outputting.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram for explaining the operation of the address counter of the present embodiment, FIG. 3 is a diagram for explaining the operation of the present embodiment, and FIG. FIG. 4 is a diagram for explaining an operation of storing image data in a memory according to the embodiment.

In this embodiment, an image memory 11 for storing image data, a write address control circuit 13 for setting and controlling a write address of the image memory 11, and a read for setting and controlling a read address of the image memory 11 are provided. The image memory 11 includes an address control circuit 14, an interrupt generation circuit 12 for notifying the CPU 15 that the writing of one line has been completed, and a CPU 15 for controlling the apparatus. In addition to the data for the page, data corresponding to the data between the first and second pages (the data amount is one page) is stored in advance.
By overwriting two pages of image data later, a continuous one-page spread image is output at the time of recording and outputting.

Next, the operation of this embodiment will be described. Image data is received from a terminal 101, a one-line valid signal is received from a terminal 102, and a write clock is received from a terminal 103. As the image data, the image data indicated by the dotted line in FIG. 3 is received first, and then the first page and the second page are received. As a condition, in the image data of the dotted line portion in FIG. 3, the portion overlapping the first page and the second page is white data. In each of the three receptions, an interrupt is given to the CPU 15 by the interrupt generation circuit 12 to notify the CPU 15 that the reception of each line data has been completed. When this interrupt is notified to the CPU 15, the start address of the area for writing the next line data to the image memory 11 is set in the write address control circuit 13.

When reading from the image memory 11, FIG.
As shown in FIG. 4, in order to be able to read the combined image data of pages 1 and 2 as they are, it is necessary to store each data shifted in line units as shown in FIG. Thus, the write address control circuit 13 counts one line for each line based on the address notified from the CPU 15. As can be seen from FIG. 4, the second half of the first page and the first half of the second page are overwritten on the page between the first and second pages stored in the image memory 11 first. In the reading from the image memory 11, as described above, since the image is stored as a two-page spread image in the image memory 11, the reading address control circuit 14 counts sequentially from the address 0, and reads from the terminal 104 as it is in line units. I can put it out.

FIG. 2 shows a write address counter of the write address control circuit 13.
One line of valid signals is received from the terminal 103 by a write clock. Before receiving the image data from the host device, it receives a reset signal from the terminal 201 and resets the write address counter 21. When the above-mentioned one-line valid signal becomes invalid, the head address value for storing each image data on a line-by-line basis is input to the terminal 202.
And sets it in the write address counter. Then, when the valid signal of the next one line becomes valid, the write address is output from the terminal 203 to the image memory 11.

[0011]

As described above, the present invention provides an image memory for storing image data, a write address control circuit for setting and controlling a write address of the image memory, and a read address for setting and controlling the image memory. A read address control circuit, an interrupt generation circuit for notifying the CPU of completion of writing of one line to the CPU, and a CPU for controlling the operation of each of the above-described units, thereby reducing the first and second pages. During this period, the image data of another page is first received and stored in a predetermined image memory, so that a continuous double-page spread can be recorded.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram illustrating a write address counter according to the embodiment;

FIG. 3 is a diagram for explaining the operation of the present embodiment.

FIG. 4 is a diagram for explaining an operation of storing image data in a memory according to the embodiment;

[Explanation of symbols]

 11 Image Memory 12 Interrupt Generation Circuit 13 Write Address Control Circuit 14 Read Address Control Circuit 15 CPU 16 Write Address Counter

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 1/387-1/393 H04N 1/21

Claims (1)

(57) [Claims] An image memory for storing image data, a write address control circuit for setting and controlling a write address of the image memory, a read address control circuit for setting and controlling a read address of the image memory,
An interrupt generation circuit for notifying the CPU of completion of writing of one line to the CPU, and a CPU for controlling the operation of each section are provided .
In addition to the data for the page, the data between the first and second pages
Store the amount of data for one page, and output it when recording.
An image processing apparatus for outputting continuous one-page spread image data .