JP2874437B2 - Image processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus.

[0002]

2. Description of the Related Art Image processing apparatuses are widely used not only by general facsimile machines but also by companies that issue publications such as newspaper companies and printing companies. Among them, newspaper companies use image data for one page received via a communication line as it is.
It was output in sheets. That is, when one page of image data is stored in the image memory of the image processing apparatus, the image data is read from the image memory in units of one line.

[0003]

However, in the above conventional example, as soon as one page of image data is stored in the image memory of the image processing apparatus, the image data is read out from the image memory in units of one line. Therefore, there is a disadvantage that image data for two facing pages cannot be output by one sheet like newspaper.

[0004]

SUMMARY OF THE INVENTION An object of the present invention is to provide an image processing apparatus which can solve the disadvantages of the prior art and can output image data of a plurality of pages as one sheet.

[0005]

Therefore, according to the present invention, there is provided an image memory for storing a plurality of pages of image data via a communication line, a write address and a read address output to the image memory, and an image for one line. A memory control circuit that outputs a read end signal when data is read, a line enable generation circuit that outputs a line enable signal that instructs the memory control circuit to read one line of image data, and a read end from the memory control circuit A CPU that outputs the start address of the next line to be read out to the memory control circuit by a signal . I
The line enable generation circuit ends the fixed count
The recording start time to turn off the line enable signal later
Counter and the number of one-line image data from the CPU.
And after the end of the recording start counter
A line counter for starting counting operation, and
After the start counter finishes counting, the line counter
Outputs the operation start command and
Turn the line enable signal “ON” after counting is completed.
It adopts a configuration called and an that timing output control circuit. This aims to achieve the above-mentioned object.

[0006]

[Action] (1). Write operation to image memory:

[0007] A counter clear signal is input from the CPU to the memory control circuit and is cleared. An image data section signal and a write image data clock are input from the CPU to the memory control circuit. When image data is input to the image memory from the communication line, the image data section signal is simultaneously turned on, and the memory control circuit outputs the write address to the image memory in synchronization with the image data clock for writing. In the image memory, the image data is stored in synchronization with the write image data clock in order from the write address from the memory control circuit.

(2). Read operation from image memory:

A reset signal is output from the CPU to the line enable generation circuit. At this time, the line enable signal output from the line enable generation circuit is "ON".
It is. The CPU inputs the head address of the first line of the first page and the read image data clock to the memory control circuit. The number of image data of one line is input from the CPU to the line enable generation circuit. The data of the recording start position and the phase signal designating the image position of one line are input from the CPU to the line enable generation circuit. The line enable generation circuit turns off the line enable signal after counting a certain number of times.

When the line enable signal is turned off, the memory control circuit outputs a read address to the image memory in synchronization with the read image data clock. The image data of the first line of the first page is read from the image memory sequentially from the read address position from the memory control circuit in synchronization with the read image data clock. Line enable generation circuit turns off line enable signal
After that, when the number of one-line image data is counted, the line enable signal is turned "ON" and output to the memory control circuit to stop outputting the read address to the image memory. Then, the output of the image data from the image memory also stops. At the same time, the line enable signal is output to the CPU as a read end signal. Upon receiving the read end signal, the CPU stores the start address of the first line of the second page in the memory control circuit by interrupt processing. Hereinafter, the above processing is repeated.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS.

In the embodiment shown in FIG. 1, an image memory 11 for storing image data for a plurality of pages via a communication line, a write address and a read address are output to the image memory 11, and one line of image data is read. A memory control circuit 13 for outputting a read end signal, a line enable generation circuit 12 for outputting a line enable signal for instructing a timing to read one line of image data to the memory control circuit 13, and a read from the memory control circuit 13. And a CPU 14 for outputting the head address of the next line to be read out to the memory control circuit 13 in response to the end signal.

Here, the line enable generation circuit 12
As shown in FIG. 2, a recording start counter stores the recording start position data from the CPU 14, starts the operation by a phase signal designating the image position of one line, and turns off the line enable signal after the count is completed. 2
2, a line counter 21 that stores the number of one-line image data from the CPU 14 and starts operation after the count of the recording start counter 22 ends, and outputs an operation start command to the line counter 21 after the count of the recording start counter 22 ends. And a timing output control circuit 23 for turning on the line enable signal after the count of the line counter 21 is completed.

Further, the memory control circuit 13 is cleared by a counter clear signal, operates only when the image data section signal is "ON", and outputs a write address in synchronization with a write image data clock. And a read address counter 32 which stores the line head address from the CPU 14 and operates only when the line enable signal is "OFF" and outputs the read address in synchronization with the read image data clock.

Next, the operation of this embodiment will be described.
Here, a case where two pages of image data are output as one sheet will be described as an example.

(1). Write operation to image memory 11:

[0017] A counter clear signal is input from the CPU 14 to the write address counter 31 via the terminal 302, and the write address counter 31 is cleared.

[0018] An image data section signal is input from the CPU 14 to the write address counter 31 via the terminal 301. Further, a write image data clock is input from the CPU 14 to the write address counter 31 via the terminal 303.

[0019] When image data is input to the image memory 11 from the communication line via the terminal 101, the image data section signal is turned on at the same time, and the write address counter 31 starts counting operation and outputs the write image data clock. Synchronize write address with terminal 30
7 to the image memory 11.

[0020] The image memory 11 stores the image data in order from the write address sent from the write address counter 31 via the terminal 307 in synchronization with the image data clock for writing. That is, the image data is stored in order from the address 0 of the image memory 11 as shown in FIG. 4, and the second page is stored after the first page.

(2). Read operation from image memory 11:

[0022] First, the CPU 14 via the terminal 204
, A reset signal is output to the recording start counter 22, the line counter 21, and the timing output control circuit 23.
At this time, the line enable signal output from the timing output control circuit 23 is “ON”.

The head address of the first line of the first page is input to the read address counter 32 from the CPU 14 via the terminal 304. Then, the read address counter 3
2 is stored.

The read image data clock from the CPU 14 via the terminal 306 is supplied to the read address counter 3.
2 is input.

[0025] 1 from the CPU 14 via the terminal 201
The number of lines of image data is input to the line counter 21. Then, it is stored in the line counter 21.

[0026] Data at the recording start position is input from the CPU 14 to the recording start counter 22 via the terminal 202. Then, it is stored in the recording start counter 22.

[0027] When a phase signal designating an image position of one line is input to the recording start counter 22 via the terminal 203, the recording start counter 22 performs a counting operation.

When the count operation is completed, the recording start counter 22 turns off the line enable signal and notifies the timing output control circuit 23 of the end of the count. Then, the timing output control circuit 23 operates the line counter 21 subsequently.

[0029] When the line enable signal is turned off, the read address counter 32 starts a count operation and outputs a read address from the terminal 308 to the image memory 11 in synchronization with the read image data clock.

[0030] The image data of the first line of the first page is sequentially read from the image memory 11 in synchronization with the read image data clock from the read address position transmitted from the read address counter 32 via the terminal 308, and from the terminal 102. Is output.

[0031] When the counting operation ends, the line counter 21 notifies the timing output control circuit 23 of the end of counting.

[0032] When the timing output control circuit 23 receives the count end notification from the line counter 21, it turns on the line enable signal as shown in FIG. 6 and outputs the signal to the read address counter 32 of the memory control circuit 13 via the terminal 205. Then, the output of the read address from the read address counter 32 to the image memory 11 is stopped. Then, the output of the image data from the image memory 11 also stops.

At the same time, the line enable signal is supplied to the terminal 309.
Is output to the CPU 14 as a read end signal.

[0034] Upon receiving the read end signal, the CPU 14 stores the start address of the first line of the second page in the read address counter 32 of the memory control circuit 13 by interrupt processing as shown in FIG.

Thereafter, the above processing is repeated.

When the image data of the first line of the first page is output as described above, the image data of the first line of the second page is output, and then the image data of the second line of the first page is output. The data is output in the order of the image data of the second line of the second page,....

[0037]

Since the present invention is constructed and functions as described above, according to the present invention, the output of image data can be controlled line by line, and therefore, image data over a plurality of pages can be converted into one image. It is possible to provide an unprecedented excellent image processing apparatus capable of outputting an image.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention.

FIG. 2 is a detailed configuration diagram of a line enable generation circuit in FIG. 1;

FIG. 3 is a detailed configuration diagram of a memory control circuit in FIG. 1;

FIG. 4 is an explanatory diagram for explaining a storage area of an image memory in FIG. 1;

FIG. 5 is a timing chart for explaining the operation of the CPU in FIG. 1;

FIG. 6 is a timing chart for explaining an operation of the line enable generation circuit in FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Image memory 12 Line enable generation circuit 13 Memory control circuit 14 CPU 21 Line counter 22 Recording start counter 23 Timing output control circuit 31 Write address counter 32 Read address counter

Claims (1)

(57) [Claims] 1. An image data for a plurality of pages via a communication line.
Image memory for storing data and writing to this image memory.
Output read address and read address.
Outputs read end signal when image data for IN is read
Memory control circuit, and one line
Line that indicates the timing to read the image data
A line enable generation circuit for outputting an enable signal;
A read end signal from the memory control circuit.
Memory control the start address of the next line to be read next
Equipped with a CPU to be output to the circuit, the line enable generating circuits, said recording start stores a recording start counter to "off" the line enable signal after a predetermined count completion, the number 1 line image data from the CPU A line counter for starting a counting operation after the counting of the counter is completed, and a timing for outputting an operation start command to the line counter after the counting of the recording start counter is completed and for turning on a line enable signal after the counting of the line counter is completed images processor characterized by being composed of an output control circuit.