JPH047966A - Printer controller - Google Patents

Abstract

PURPOSE:To obtain the printer controller to synchronize with a picture by a CPU by providing a timing generating means, executing write and read asynchronously and providing a line buffer to store a data for one line. CONSTITUTION:A CPU 3 develops information received from a host to a picture image and stores it into a bit map memory 4. In the case of printing, the CPU 3 reads out the picture data previously stored in the memory 4 and writes the data into a line buffer 5. This buffer 5 is used so that the CPU 3 can synchronize pictures for the unit of one line, and since the synchronization is not for the unit of one byte, the CPU 3 can execute the other processing during printing. The data stored in the buffer 5 is read out by a picture synchronizing part 6 corresponding to a synchronizing signal from a printer 2, serially converted and outputted as the data for laser modulation of the printer 2.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a printer controller equipped with an image synchronization circuit that synchronizes image data from a host and sends it to a printing unit.

(Prior Art) In a dot printer such as a laser printer, a print controller receives image information such as character codes from a host such as a host computer, develops an image according to the information, and stores it in a bitmap memory. For example, when an image for one page is stored, the data is output to a printing unit to print the image on paper.

(Problems to be Solved by the Invention) As the price of laser printers decreases, printer controllers are required to decrease in price.

Printer controllers used hardware circuitry to draw dot images into memory. Some conventional hardware circuits use expensive image control LSIs and additional circuits. (This dedicated LSI
Some have DRAM line buffers. D.R.
AM performs a refresh operation even while outputting white data. ) Furthermore, there are devices that use a hardware logic circuit to synchronize with the image by DMA transfer without going through the CPU (that is, they do not have a line buffer). Therefore, in order to reduce the price of the printer controller, it is desired to simplify the hardware circuit.

Therefore, it is thought that the hardware configuration can be simplified if the CPU that controls the printer controller also controls the transfer of the image to the printing section. but,
At this time, unless the load on the CPU is reduced for the part of image synchronization with the printing unit, which requires the most stringent timing conditions, the CPU or other processing will not be able to be executed. Therefore, unless this point is solved, it is not possible to have the CPU control the transfer of image data to the printing section.

Let's consider a printer with a printing speed of 6 pages per minute and a resolution of about 300 dots/inch. In this case, the image data synchronization clock VCLK has a frequency of 1°5-2 MHz (period of 660-500 ns). It is difficult for the CPU to output image data at this speed. Therefore, a synchronization circuit is required to operate at an even lower frequency.

Now, considering that the CPU writes 8-bit parallel image data to the parallel-serial converter and outputs it to the print unit as real data, the WRREQ signal at the write timing of the C'PU has a cycle of 4 to 5.3 μs. This is a signal with a cycle that allows a general CPU to transfer data sufficiently. However, writing is done using the timing signal WR.
There is a problem in that the process must be performed within one synchronous clock VCLK after REQ is generated. This WRRE Q
Signals are difficult to detect and synchronize in software. Therefore, a method that does not involve software is required. For example, it is conceivable to provide a logic circuit exclusively for reading the bitmap memory, but since two circuits, the CPU and the logic circuit, access the bitmap memory, the circuit becomes complicated.

Another possible method is to use a READY signal provided in the CPU. In this case, the WRREQ signal is used as it is as the CPU's READY signal, and when writing data to the parallel-to-serial converter, when WRREQ (No. 11) is at the "L" level, a wait state is inserted in the CPU and the print section In this way, image data is output from the CPU to the printing unit, but while the image data is being output, that is, while printing one page, the CPU cannot perform other processing. communications from the computer may be stopped, or urgent error handling may become impossible.

An object of the present invention is to provide a printer controller that performs image synchronization using CPH.

(Means for Solving the Problems) A printer controller according to the present invention receives image information from a host, develops the image in a bitmap memory according to the information, and transmits the developed image data to a synchronization signal from a printing unit. In the printer controller, which outputs image data to the printing unit according to A data writing means reads one line of image data and writes it into the line buffer, and writes the image data of the Nth line into the line buffer without overtaking the reading of the image data of the N-1th line. The present invention is characterized in that a timing generation circuit is provided which generates a timing signal for a data write request and sends it to the data writing means so as not to be overtaken by the reading of image data of N lines.

(Function) Writing and reading are performed asynchronously, and a line buffer is provided that can store data for life.

When the data writing means receives the timing signal from the timing generating means, it writes data for one line of the bitmap memory into the line buffer asynchronously with the reading.

On the other hand, data reading from the line buffer is performed asynchronously with writing in response to a horizontal synchronization signal from the printing section.

Margin below (Example) Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

As shown in Figure 1, a dot printer such as a laser printer has a controller (image generator) 1 that converts information such as character codes received from a host such as a host combination coater into a dot image, and a dot image generator. It consists of a printer engine (printing section) 2 that prints. In this embodiment, the printer engine 2 performs printing by an electrophotographic process using a laser optical system.

The controller l is controlled by the CPU3, and
develops the information received from the host combinator into an image and stores it in the hit map memory 4. When printing, the CPU 3 reads the image data stored in the bitmap memory 4 in advance and writes it into the line buffer 5. The line buffer 5 is used by the CPU 3 to synchronize on a line-by-line basis. Since the synchronization is not performed in units of 1/item, the CPU 3 can perform other processing even during printing. The data stored in the line buffer 5 is read out by the image synchronization unit 6 in response to the synchronization signal sent from the printer engine 2, and is converted into serial data by the image synchronization unit 6 to modulate the laser of the printer engine 2. The data is output to the printer engine 2 as data for use.

Since the output of this image is used as data for modulating the laser beam that scans the photoreceptor in the printer engine 2, it is necessary to synchronize the polygon mirror, which rotates at a constant speed, with the photoreceptor. At this time, the synchronization accuracy is the image accuracy.

FIG. 2 shows the synchronization signal output from the printing section of the printer and the timing of image data in response to the synchronization signal. FIG. 3 shows the correspondence between each synchronization signal shown in the timing chart of FIG. 2 and the printing result. Here, PSYNC is a vertical synchronization signal (page synchronization signal), which falls outside the paper 21 in the vertical direction (paper feeding direction) before the start of printing one page. L
SYNC is a horizontal synchronization signal (line synchronization signal),
When PSYNC reaches the print area 22 of the paper in the vertical direction after T1 time has elapsed after the fall of PSYNC, it falls outside of the horizontal direction I (this paper 2), and then similarly starts printing each of NV lines. fall in front. VCLK is a synchronization clock for image data, and falls at a time T4 after the fall of LSYNC, and thereafter falls by the number of pixels NH in the horizontal direction of the printing area of the paper.

VDATA (di, d2...dNH) is image data and is output in synchronization with the falling edge of LSYNC. Time T5 (LSYNC signal period) and T6 (VCL
K signal periods) are each a length corresponding to the margin defined by the printer.

As shown in FIG. 3, printing is started by generating a PSYNC signal before reaching the paper 21 in the sub-scanning direction (paper feeding direction). Printing is performed within a print area 22 indicated by diagonal lines within the paper 21. Note that the sizes of the top, bottom, left and right margin portions 23 are defined by the printer. At the beginning of each line, a synchronizing signal LSYNC is generated outside the paper 21, and within the printing area 22, a synchronizing signal VCLK is generated corresponding to each pixel.
A signal is generated, data VDATA is sent in response, and printing is performed.

FIG. 4 is a circuit diagram of the line buffer 5 and the image synchronization section 6.

As line buffer 5, first-in-first-out memory (hereinafter referred to as FI) is used to simplify the peripheral circuitry.
(referred to as FO memory) 41 is used.

In the FIF◯ memory 41, the reading side and the writing side operate asynchronously, and the data written first is read out. In the FIFO memory 4I used here, an address signal is generated internally, and after the address is set to 0, the address is incremented by 1 each time a write operation or a read operation is performed. Therefore, there is no need to generate an address signal when accessing the FIFO memory 41. Further, since the reading side and the writing side are independent, the CPU 3 only needs to write one line of image data in the bitmap memory 4 regardless of reading. On the reading side, the image data may be read from the FIFO memory 41 in synchronization with the synchronization signal LSYNC from the printer engine 2, and the serially converted video data VDATA may be output in synchronization with the synchronization signal VCLK sent from the printer engine 2.

The image synchronization unit 6 includes a shift register 42 that converts the image data (8-bit parallel) read from the FIFO memory 41 into a serial video signal VDATA in synchronization with the serial video clock VCLK, and a shift register 42 that divides the frequency of the serial video clock VCLK by 8. A read timing generation circuit 43 generates a read signal RD for the FIFO memory 41 based on the horizontal synchronization signal LSYNC, and a FIF generates a timing signal WRREQ for writing to the FIFO memory 41 based on the horizontal synchronization signal LSYNC.
It is composed of an O control timing generation circuit 44.

FIG. 5 is a circuit diagram of the read timing generation circuit 43. The read timing generation circuit 43 is composed of a 3-bit counter 6I and an AND gate 62. Counter 61 counts VCLK and 3-digit binary signal Q2. Ql
, outputs QO. The counter 61 is also reset by the LSYNC signal at the beginning of each line. Next, VCLK
When the signal is input, the counter 6I is incremented by I. AND gate 62 receives binary output signal Q2,
Find the product of Ql and QO and output RD.

That is, RD-0 is output only when the count value is 1n.

As a result, a read timing signal RD is generated every 8 bits (1 byte).

The FIFO control timing generation circuit 44 includes a counter, and upon receiving the horizontal synchronization signal LSYNC, counts a predetermined number of VCLK signals and outputs WRREQ as described later.
This is a delay circuit that outputs a signal to the CPU 3, and outputs the write timing signal WRREQ of the FIFO memory 41 to the CP
Output to U3.

As a simple method, the one-shot multivibrator may be triggered by the LSYNC signal. Figure 6 shows the timing of writing and reading from the FIFO memory 4I, and Figures 7 and 8 show the timing of writing and reading from the FIFO memory 4I. The timing of writing to and reading from the FIFO memory 41 will be shown in more detail.

After the writing of one line of data to the FIFO memory 41 is started, the reading of that one line of data is started.

On the write side of the FIFO memory 41, the CPU 3
When it detects that the EQ signal is active,
Set the write address of the FIFp memory 41 to 0 and set it to 124.
Write 2 minutes of image data to the FIFO memory 41 (7th
(see figure).

Note that the WR and WRCLR signals are hFrF, respectively.
o The address for writing to the memory 41 and the address for clearing the write address of the FIFO memory 41 are allocated to the memory space of the CPU 3, and the WR of the CPU 3
A signal obtained by ANDing signals that become active when the address of each double signal is detected may be used. C.P.
U3 first clears the write address and then sequentially writes the data for the ] line, but the write address is incremented at the rising edge of the WR times signal.

On the read side, LSYNC, VCLKf: synchronously with FI
Image data is read from the FO memory 41 (see FIG. 8). When the LSYNC signal is input, the FI
The read side address of the FO memory 41 becomes O, the 3-pint counter 61 for generating the RD times signal is also cleared, and the shift register 42 is also cleared. Then, the image data of the first byte (address 0) is loaded into the shift register 42.

Thereafter, the counter 61 is incremented at the falling edge of the VCLK signal, and when the count value is 1, the RD times signal becomes active. This signal is used as a clock for reading out the FIFO memory 41, and also as a clock for reading out the FIFO memory 41.
It is used to load data read from memory 41 every 8 bits.

The shift register 42 converts the 8-bit parallel data read from the FIFO memory 41 into a serial video signal and outputs it to the printer engine 2. That is, this shift register 42 is cleared (own data) when LSYNC is input, and when the RD double signal is at L level, the VC
The data from the FIFO memory 41 is loaded at the rising edge of LK, and when the RD double signal (■) is at the level, the data is shifted one bit at a time at the rising edge of VCLK.

By performing line-by-line synchronization using the line buff 75 in this manner, the CPU 3 can easily synchronize with the printer engine 2, and the load on the CPU 3 can be reduced. For example, with a CPU 18086 that operates with an operating clock of 8M) (2), if the fastest data transfer instruction MOVSB is used, the data transfer time for n bytes is 9 + (
If the resolution is 300 dpi and the length in the main scanning direction is 8.5 inches, then one line (=3
19 bytes) data transfer time is 9+(17×319
)-2242 clock, so it is 280 ps. This is 1.3 to 1,7 when synchronizing in 1 byte units.
This is a very small value compared to ms. Therefore, L.S.
Considering that the YNC cycle is about 2-2.5ms, the time required to transfer image data is about 10%,
The CPU 3 will be able to perform other processing as well.

Moreover, the timing of writing to the line buffer 5 does not have to be constant, and it is sufficient to satisfy the condition that the data be written before being read. In other words, writing on the Nth line is
It is fine as long as it is not overtaken by line reading.

By using the FIFO memory 41 for one line in this way, it is possible to omit unnecessary synchronization in byte units and also to enable flexible writing.

Next, the determination of the write start timing will be explained.

In the timing chart of Figure 6, for easy understanding,
Although the writing of the N+1 line starts after a certain period of time after the start of reading the Nth line, it is not necessary to wait for a certain period of time. Data of the m-th byte of the n+1 line may be written. In other words, the reading of the Nth line is
It is fine as long as the writing on the line does not overtake it.

The time required to write one line of data [W is
It may be shorter or longer than the printing period of one line.

Combining the above-mentioned conditions, the conditions for writing the Nth line are (1) not to overtake the reading of the N-1th line, and (2) not to be overtaken by the reading of the Nth line.

An extreme example satisfying the above conditions is shown in FIG.

In this case, writing of the N+1th line started while reading the Nth line, but was interrupted twice due to other interrupt processing (see the hatched part). However, this is a case where the condition ``not being overtaken by read processing'' mentioned above is also satisfied.

In the write timing, the timing with the most margin for reading is to detect the end of reading of the m-th byte of the N-th line and write the m-th byte of the N+1-th line.

However, this method only performs byte-by-byte synchronization, which consumes a lot of wasted time and requires detection that the m-th byte is being read. This wasted time can be used for other processing, resulting in poor processing efficiency.

Therefore, in the present invention, the following method is used.

First, the time T required to write image data for one life in the minimum time is determined. The timing tNend at which reading of each line ends is determined. Based on the above two, the write start timing for the N+1 line is set as follows. In other words, the write start timing tN, 5trt of the N+1 line is set to a time T earlier than the read end timing tNend of the Nth line (tN+, 5t).
rt+T)tNend).

With this setting, condition (2) is definitely satisfied, there is sufficient margin for condition (2), and CPU3 is
After detecting t, it becomes possible to continuously write data to the FIFO memory 41 using the most efficient method, and sufficient time is available for other processing.

The FIFO timing generation circuit 44 uses the timing determined in this way as a synchronization signal L for reading from the printing section.
The clock VCLK is generated by counting a predetermined number of times from the SYNC.

In addition, when interrupting writing as in the case of data writing in FIG. 9 or FIG. 13 (described later), condition ■ is satisfied;
Please consider this.

Next, line buffer 5 has a FIF consisting of DRA and M.
An example using O memory will be described.

DRAM has a high degree of integration and is suitable for compact systems. Therefore, it is preferable to simplify the hardware configuration of the printer controller.

However, in general, the circuit becomes complicated due to the following reasons.
Unless the part requires a certain amount of storage capacity, SR
AM results in a more compact system. Therefore,
When using DRAM, it cannot be used in a print controller unless consideration is given to making the circuit more compact.

In DRAM, each storage unit has a capacitor, and information is stored depending on the presence or absence of charge stored in the capacitor. This charge leaks over time and must be recharged within a specified time. This is called a refresh operation. Generally, this specified time is 4ms for 256-bit DRAM and 4ms for LM bit DRAM.
M is about GMS. In special cases, 1m
In some cases, only s is guaranteed.

There are various methods for this refresh operation, but in order not to degrade the performance of the circuit, it is conceivable to add a circuit dedicated to refresh. However, in a line buffer circuit like the present invention, in which the read side and the write side operate asynchronously, it is necessary to detect the timing when neither reading nor writing is being performed, and perform a refresh operation during that time. The drawback is that it requires a complicated circuit.

By the way, when the data to be stored is only temporarily required as in the present invention, the refresh operation itself can be omitted. In other words, the data written in the line buffer 5 may be output to the printer engine 2 within a specified time.

That is, in order to make a refresh operation unnecessary, when the writing side detects the write control timing, it writes one line of data to the line buffer 5 continuously as quickly as possible. On the reading side, the line buffer 5 is read in accordance with the synchronization signal sent from the printer engine 2. At this time,
The timing of writing and reading is controlled so that the time from writing image data to reading that data is always within the data retention time of the DRAM.

By the way, if the DRAM is not refreshed at all, all the charges stored in the capacitors constituting the DRAM will be discharged. If the polarity of the output of each bit when discharged is determined so that it becomes "white data" in the image, if there is no refresh at all, the print result may be white where it should be printed black, but The opposite is not true. Therefore, when the own data continues over multiple lines, once the white data is written to the line buffer 5, it is not necessary to refresh until the next black data appears, and it is also necessary to write the own data on each line. None.

During this time, although the CPU 3 of the print controller needs to count and manage the number of lines, it is not necessary to write the image data to the line buffer 5, so it can perform other processing. For example, in the example shown in FIG.
Printing is performed only on the shaded areas on the paper. Therefore A.

Each line in the portions B, C, and D contains only white data, so there is no need to refresh it. Especially after outputting the data of the last line of black data of each page (part D in Figure 11), there is no need to control the line buffer 5, and for example, start editing the data of the next page. can do.

In actual DRAM, the output when not refreshed is
In some cases, all the hits are the same, and in others, as shown in Table 1, they are determined by the address signal.

Below is a margin Table 1 Data polarity When the DRAM shown in Table 1 is not refreshed (all DRAM data is #0''), the polarities of the A7 and AO signals among the address signals AO-A7 are the same. If so, it outputs "o", and when the polarities of the A7 and AO signals are different, it outputs "l".

In the case of the DRAM shown in Table 1, by providing a circuit as shown in FIG. 1O, the polarity of the output when not refreshed can be made uniform.

In the circuit of Fig. 10, the FIFO memory 80 is used as DRAM.
is used to connect the input terminal of the FIFO memory 80 and the data input D
A 3-state buffer 81 and an inverter 82 are connected in parallel between the FIFO memory 80 and the data output DOUT, and a 3-state buffer 83 and an inverter 84 are connected in parallel between the FIFO memory 80 output terminal and the data output DOUT. On the other hand, CPU
Address signals A7 and AO from 3 are EXOR gate 85
and its output is input to the 3-state buffer 81°8.
The signal is inverted and input to the ENi terminal of 3-state inverter 82 and 84, and is also inverted and input to the EN terminal of 3-state inverter 82 and 84 via inverter 86.

When the input data is being processed, the input data is output as is, as shown in Table 1.

That is, when the polarities of the address signals A7 and AO do not match, the output of the EXOR gate 85 is "l'", so that the EN terminal of the 3-state inverter 82 is "1".
1" is input and 'O" is input to the EN terminal of the 3-state buffer 81, so the data input to the data input DIN is inverted by the 3-state inverter 82 and input to the PIF080 memory. Therefore, the inverted data is stored in the FIFO memory 80, and at the time of output, it is inverted again by the 3-state inverter 84, returned to its original form, and outputted to the data output DOUT.

On the other hand, when the polarities of the signals at addresses A7 and AO match, the output of EXOR gate 85 is "o", so 3-
The state inverters 82 and 84 do not operate, and the data input to the data input DTN is transferred to the 3-state buffer 81.
The signal is input to the FlF○ memory as is through the 3-state buffer 83, and is output as is to the data output DOUT.

Sometimes, when the data is not refreted or unused (all data in the line buffer 80 is HO''), the FIFO memory 80 outputs ``L'' at addresses where the polarities of the A7 and AO signals do not match, but 3 -state inverter 8
4 and outputs 70' to the data output DOUT, and 0 at the address where the polarity of the A7 and AO signals match.
``'' is output as it is through the 3-state buffer 83 and output as 0'' to the data output DOUT, so when refresh is not performed, ``o'' is output to the data output DOUT at all addresses.

Next, how to determine the write start timing for the FIFO memory 80 made of DRAM will be described below. In this case, in addition to the above conditions (1) and (2), the prescribed refresh time t0 must also be taken into consideration. Writing should be performed as continuously as possible.

(1) When the time t required to write image data for 1 life is shorter than the time R required to read 1942 minutes of data (see FIG. 12).

If data writing for each line is completed after a time that is the data retention time L0 of the DRAM before the time at which the last data of each line is read, the refresh operation becomes unnecessary. Therefore, the time from the time when the last data of each line is written to the time when that data is read is 1. , t.

<to. The writing start time may be set earlier than the writing end time by the time tW required to write one line of data.

Also, if the time required to write is 1w75-too short,
The write start time that satisfies this condition may be after the read start time for each line, which may violate condition (tR>t
, +tl). In this case, the write process for each line may be divided into a plurality of processes, and the write start time of each process may be determined so that the conditions (1) and (2) described above are satisfied.

For example, as shown in FIG. 13, the time t required to write 1942 minutes of image data is divided into two sections twl,
The write request timing signal W is divided into tw2 (Lwt 10'W2='W), and a delay circuit is provided corresponding to each of them.
RREQI.

Generate WRREQ2. The CPU 3 performs write processing in two sections in response to these two timing signals.

(2) Time t required to write one line of image data
When W is longer than the time R required to read data on line 1 (see FIG. 14).

The data write start time of each line is set to be a time t1 shorter than the data retention time t0 of the DRAM before the read start time of each line.

(Effects of the Invention) Conventionally, a hardware logic circuit or a dedicated LSI was required for the printer controller, but the synchronization of image data transfer with the print section of the printer is now synchronized line by line using a line buffer. Take, CP
It is now possible to transfer data from U. This simplifies the circuit, improving reliability and reducing costs.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the printer. FIG. 2 is a timing chart of various synchronization signals. FIG. 3 is a diagram showing the relationship between synchronization signals and printing paper. FIG. 4 is a circuit diagram of the line buffer and image synchronization section. FIG. 5 is a circuit diagram of the read timing generation circuit. FIG. 6 is a timing chart of writing and reading from the FIFO memory. FIG. 7 and FIG. 8 are timing charts for writing and reading from the FIFO memory, respectively. FIG. 9 is a timing chart for explaining the relationship between writing and reading. FIG. 1O is a diagram of a DRAM polarity alignment circuit. FIG. 11 shows an example of the area of printing. FIG. 12, FIG. 13, and FIG. 14 are all timing charts for writing to and reading from the line buffer. 1... Controller, 2... Glinter engine, 3... CI), 5... Line buffer (DRAM), 6... Image synchronization unit. Patent Applicant Minolta Camera Co., Ltd. Agent Patent Attorney Aohaku Ao and 2 others No. 3 Tofu

Claims (1)

[Claims] (1) In a printer controller that receives image information from the host, develops the image in a bitmap memory according to the information, and outputs the developed image data to the printing section, stores and writes one line of image data. A line buffer that reads data asynchronously and reads the data written first; a data writing means that reads one line of image data from the bitmap memory and writes it to the line buffer; data reading means for reading image data from a line buffer in accordance with a horizontal synchronizing signal outputted prior to printing; In order to avoid being overtaken, the timing signal of the data write request for writing the image data of the Nth line to the line buffer is set at a predetermined timing corresponding to the horizontal synchronization signal of the N-1th line from the printing unit. A printer controller characterized in that it is provided with a timing generation circuit that generates a timing signal and sends it to data writing means.