JP2922660B2 - Image processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus such as a laser beam printer , and more particularly to an image processing apparatus having a first printing density.
Converting the image data into high-density image data of a second print density,
Image processing for outputting an image based on the converted image data
Related to the device .

[0002]

2. Description of the Related Art In recent years, laser beam printers have been widely used as output devices for computers. In particular, 3
Small machines having a resolution of about 00 dpi (dots / inch) are rapidly becoming popular due to their advantages such as low cost and compactness.

As shown in FIG. 13, a laser beam printer includes a printer engine unit 201 for actually printing on a photosensitive drum based on dot data, and an external host computer 20 connected to the printer engine unit 201.
The printer controller 202 receives the code data sent from the printer engine 3, generates page information including dot data (bitmap data) based on the code data, and sequentially transmits the dot data to the printer engine unit 201. The host computer 203
Floppy disk 20 having application software
4 loads a program, starts the application software, and functions as, for example, a word processor.

Next, the process of a printing operation in the printer controller 202 will be described with reference to FIG.

In FIG. 1, reference numeral 114 denotes an image memory for storing bit map data (image data) for one page;
Reference numeral 115 denotes an address generator for generating an address of the image memory 114; 116, an output buffer register for converting image data read from the image memory 114 into an image signal VIDEO; 117, a well-known beam detector which is a horizontal synchronizing signal. A synchronous clock generating circuit 118 for generating an image clock signal VCLK synchronized with the signal BD;
Is a CPU that controls the entire controller, 119 is a printer i / F that is an input / output unit for signals with the printer engine 201, and 120 is a host i / F that is an input / output unit for signals with an external host such as a personal computer. is there.

An operation of transmitting the image signal VIDEO to the printer engine in the above configuration will be described.

When the printer controller 202 prepares image data for one page in the image memory 114, the printer controller 201 sends a print request signal PR to the printer engine 201.
Send INT. The printer engine 201 uses this PR
When the INT signal is received, the printing operation is started, and when the vertical synchronization signal VSYNC is received and printing can be performed, the VSREQ signal is sent to the printer controller 202. The printer controller 202 is VS
When the REQ signal is received, a vertical synchronization signal VSYNC is sent to the printer engine 201, and the V synchronization signal VSYNC is output from a predetermined position in the sub-scanning direction.
A predetermined time from the SYNC signal is counted. When the counting of the predetermined time is completed, the address generating section 115 sequentially generates an address from the head address of the image data stored in the image memory 114 and reads out the image data. The read image data is input to the output buffer register 116 for each main scanning line. In the output buffer register 116, in order to perform printing from a predetermined position in the main scanning direction, the BD buffer is provided for each print line.
After a predetermined pulse count of the image clock signal VCLK after the signal is input, the data of this print line is
It is sent to the printer engine 201 as an image signal VIDEO synchronized with the CLK signal. The printer engine 201 performs the above-described image forming operation.

By performing the above operation for each print page, printing is always performed at the same position on the paper.

[0009]

However, in recent years, high-definition print output has been demanded, and a laser beam printer is no exception. Therefore, it is conceivable to increase the resolution of the laser beam printer,
For example, when the resolution is set to 600 dpi which is twice as large as 300 dpi, the capacity of the image memory required for the printer controller is quadrupled as compared with the case where the resolution is 300 dpi, and there is a disadvantage that the cost becomes high. Also, if an attempt is made to obtain a printing speed equivalent to that at 300 dpi, the output frequency of image data is quadrupled, so that the printer controller must also operate at quadrupled speed, resulting in disadvantages in both technology and cost. Will happen. On the other hand, when considering application software, most of the software designed for a resolution of about 240 to 300 dpi occupies 600 dpi.
Even if a printer for i is made, there is a problem that these application softwares cannot be handled. Therefore,
It is necessary to make use of the above-mentioned application software and to make print output highly precise.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks of the prior art, and has been made in consideration of the above-mentioned problems.
The image data of the first print density is stored in the storage means for a plurality of lines, and the image data of the first print density is converted into the image data of the second higher print density by referring to the stored image data. By storing the white data sent before the image data for printing is sent from the printer controller in the storage unit, the storage unit is initialized, thereby achieving a low-cost, high-quality image. It is an object of the present invention to provide an image processing device capable of obtaining an output.

[0011]

Means for Solving the Problems The above-mentioned problems are solved,
To achieve the object, an image processing apparatus according to the present invention, up
Based on the image data sent from the printer controller
An image processing apparatus for outputting an image
Receiving the synchronization signal sent from the
The first print sent after a predetermined time has passed since the synchronization signal
Input means for inputting image data of density, and the input means
Stores the image data input in step 2 for multiple main scanning lines
Storage means, and image data stored in the storage means
From the image corresponding to the pixel of interest and its surrounding pixels
Reference means for referring to data, and reference result of the reference means
Based on the image data corresponding to the pixel of interest
A second printing density higher in printing density than the first printing density;
Conversion processing means for converting the image data into image data;
Output an image based on the image data converted by the
Output means for outputting the first print after receiving the synchronization signal
Of the predetermined time until image data of the density is sent.
White image sent from the printer controller in the meantime
By storing data in the storage means,
Control means for initializing the storage means.
I do.

[0012]

According to this configuration, the first input by the input means is performed.
Storage means for storing image data having a printing density of
From the image data stored in the
Referring to the image data corresponding to the pixels surrounding the pixel,
The first printing density higher than the first printing density.
The image data is converted into image data having a print density of 2. Where the memory hand
Sent from printer controller to initialize stage
Uses white image data.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

(First Embodiment) A first embodiment according to the present invention will be described for a case of a 300 dpi laser beam printer.

FIG. 1 is a block diagram showing a first embodiment in which the image processing apparatus according to the present invention is applied to a laser beam printer. The printer shown in FIG.
05, a printer engine 201, a printer controller 202, and a transmission circuit 206. The signal processing circuit 205 according to the present embodiment is functionally located between the printer engine 201 and the printer controller 202 and outputs a signal 300 output from the printer controller 202.
The resolution of the image signal of dpi (hereinafter, referred to as “VIDEO signal”) in the main scanning direction is increased to 1200 dpi, and is sent to the printer engine 201 as a smoothed signal (hereinafter, referred to as “SVDO signal”).

Next, other input / output signals of the signal processing circuit 205 will be described. First, as input signals from the printer controller 202, there are a VIDEO signal, a vertical synchronization signal (hereinafter, referred to as "VSYNC signal"), and a signal (hereinafter, referred to as "SON signal") for specifying ON / OFF of smoothing processing. An input signal from the printer engine 201 is a horizontal synchronizing signal (hereinafter, referred to as a “BD signal”). Next, as an output signal to the printer controller 202, a VIDEO output clock is output.
There is an image clock signal (hereinafter referred to as "VCLK signal") synchronized with the signal. Further, the CLK signal input from the oscillation circuit 206 is a signal used as a basic clock in the signal processing circuit 205, and has a frequency eight times that of the VCLK signal. The VCLK signal is obtained by converting this CLK signal to B
Since it is created by dividing the frequency by 8 at the timing synchronized with the D signal, the synchronization accuracy for the BD signal is 1/8 of its own cycle. Therefore, the deviation (jitter) of the image in the main scanning direction with respect to the BD signal is kept within 1/8 of one dot, and a good image quality can be obtained.

Next, the signal processing circuit 205 according to the present invention will be described.

FIGS. 2 and 3 are block diagrams showing the configuration of the signal processing circuit 205 according to the first embodiment. FIGS. 4 and 5 are timing charts showing the relationship between the synchronization signal and the image data in the first embodiment. FIG. 6 is a timing chart for explaining the operation of the memory control circuit according to the first embodiment, and FIGS. 7 and 8 are diagrams for comparing and explaining data before and after the conversion of print density.

In FIGS. 2 and 3, reference numeral 1 denotes an input / output control circuit for controlling each of the above input / output signals. 2 is a static RA having a memory capacity of 8K words × 8 bits.
M (hereinafter referred to as "SRAM"), 3 an address counter for generating an address of the SRAM 2, 4 a latch having a three-state output, 5 a memory control circuit for controlling the SRAM 2, the address counter 3 and the latch 4, 6
Reference numerals 12 to 12 denote shift registers, 13 denotes a smoothing logic circuit, 14 denotes a parallel-serial conversion circuit, and 15 denotes a D flip-flop (hereinafter referred to as "D-FF").

Next, the operation of the above configuration will be described.

In the same manner as described in the conventional example, the printer controller 201 synchronizes with the VSYNC signal and sets the VID for one page from the timing after a predetermined time T1 has elapsed.
The transmission of the EO signal is started. This VIDEO signal is "white" data except during the output period. VSYN
FIG. 4 shows the relationship between the C signal and the VIDEO signal. On the other hand, the main scanning direction is synchronized with the horizontal synchronizing signal BD for a predetermined time T2.
Transmission of image data for one line in the main scanning is started from the timing after the lapse. In the above, the printer controller outputs image data in synchronization with the falling edge of the image clock signal VCLK. On the other hand, the signal processing circuit 20
In step 5, the D / FF 15 latches the image data at the falling edge of VCLK. Subsequently, the latched image data is latched in a latch 4 by a signal LCLK obtained by delaying the VCLK signal by ／ cycle. The output Q0 is output to the input / output pin I of the SRAM 2.
/ O1 and written to a predetermined address. The written image data is read out at a timing before writing the image data in the next cycle of the VCLK signal, and is input to the input terminal D1 of the latch 4. Thus, VCL
Reading of image data and writing of the next image data are performed at the same address of the SRAM 2 within one cycle of the K signal. FIG. 6 shows the timing of the above operation. When one main scanning line is completed, a reset signal (hereinafter referred to as “RS
T ") (created at the beginning of the BD signal for the next main scan), the address counter 3 is reset. Immediately after this reset, the same operation is performed for the data of the next line. Accordingly, data is written as white data in the SRAM 3 also in a period of T2 in FIG. 5 which is a non-output period of image data. That is, data from the time when the reset of the address counter 3 is released (invalid in this period, that is, "white") is treated as image data. By repeating the above operation, the image data at the same position for seven consecutive main scanning lines are simultaneously output to the outputs Q0 to Q6 of the latch 4. In the above operation, after input of the VSYNC signal, white data is written to all the addresses of the SRAM 2 during a period T1 in FIG. 4, which is a non-output period of the image data, and the SRAM 2 is initialized. The above control is performed by the memory control circuit 5.

Next, outputs Q0 to Q6 of the latch 4, which are image data for seven continuous main scanning lines, are input to shift registers 6 to 12, respectively. The shift register sequentially shifts according to the rising edge of the image clock VCLK, and a total of 49 data of seven shift outputs are input to the smoothing logic circuit 13.

The smoothing logic circuit 13 refers to image data of 7 main scanning pixels × 7 sub-scanning pixels around the printing pixel R, and divides the main scanning direction into 1200 dpi by a predetermined algorithm. Is converted into two data a, b, c, and d and output as parallel data (see FIG. 7). The above four data a, b, c and d are converted into serial data by the parallel-serial conversion circuit 14 and a clock signal 4C having a frequency four times the frequency of the image clock VCLK.
LK outputs the image signal SVDO to the printer engine as a smoothed image signal. Although the internal algorithm of the smoothing logic circuit 13 will not be described in detail, for example, in the case of 300 dpi image data from a printer controller, the oblique lines printed as shown in FIG. 8A are smoothed as shown in FIG. Printing.

The above operation is performed by the signal SO for designating ON / OFF of the smoothing process from the printer controller.
In the case where N is valid ("H"), and when the SON signal is invalid ("L"), the data of the print pixel R is output as it is. That is, when the data of the print pixel R is "black", data of "black" is output for all of a, b, c, and d, and when the data of the print pixel R is "white", a, b, c , And d output "white" data. Therefore, the output to be printed has the same result as when printing is performed by the VIDEO signal from the printer controller. By controlling the SON signal in this way, the printer controller can specify ON / OFF of the smoothing process according to the user's preference.

The signal processing circuit described above is, for example, an SRA
A portion other than M is formed into a gate array to constitute a signal processing IC with one chip, and the data output portion of the conventional printer controller board is slightly changed to convert the signal processing IC into an SR.
By adding the laser beam printer together with the AM, it is possible to provide a laser beam printer capable of obtaining a high quality image at low cost. In addition, the signal processing circuit is changed to an SRAM from
It is conceivable that the number of input / output pins is greatly reduced, and in this case, the number of input / output pins is greatly reduced.
Further, it goes without saying that the signal processing circuit may be mounted on the printer engine side.

Further, in the above embodiment, the case where the area to be referred to at the time of data conversion is 7 pixels in the main scan × 7 pixels in the sub-scan has been described, but the present invention is not limited to this.
For example, a higher quality smoothing effect can be obtained by referring to the area of 9 pixels in the main scanning × 9 pixels in the sub-scanning. Further, in the above-described embodiment, the example in which the image data of 300 dpi is converted to the data of the density image 1200 dpi in the main scanning direction is not limited to this. For example, the density is converted to the data of 2400 dpi in the main scanning direction. It can also be converted. In this case, this can be realized by using an 8-bit parallel-to-serial conversion circuit 14 and using a clock eight times VCLK as the output clock.

As described above, according to the first embodiment, the printing density of the print data of the print pixels in the main scanning direction is converted to data of four times and printing is performed, thereby achieving low cost and high quality. Image output can be obtained.

(Second Embodiment) The first embodiment described above shows a case where image data is transmitted from the printer controller 201 by a VCLK signal generated by the signal processing circuit 205. In a conventional printer controller, a transfer clock of image data synchronized with a BD signal is generally formed internally. Further, a synchronous clock generation circuit and other control circuits are provided inside a gate array. Many signals such as clock signals are not output to the outside. On the other hand, the second embodiment is
An example in which a signal processing circuit that can support the printer controller is used will be described.

FIGS. 9 and 10 are block diagrams showing a configuration example of a signal processing circuit according to the second embodiment. In the figure, circuits having the same functions as those of the first embodiment described above are denoted by the same reference numerals as in FIGS. 2 and 3, and description thereof is omitted.
In the second embodiment, the configuration different from that of the first embodiment is indicated by adding a dash to the circuit number corresponding to FIGS. A particularly different point is control of input / output signals by the input / output control circuit 1 '.

Next, signals different from those in the first embodiment will be described.

FIG. 11 is a timing chart for explaining the operation according to the signal of the second embodiment, and FIG. 12 is a circuit diagram showing the configuration of the input / output control circuit 1 'of this embodiment. In the figure, reference numerals 51, 63, and 64 denote NOT circuits, and 52 to 58.
Is D · FF, 59 and 60 are JK · FF, 61 is NAN
D circuit, 62 is a 4-bit counter, 65 to 67 are selector circuits, 62 is a 4-bit counter, and 65 to 67 are selector circuits, respectively. Configurations of parts not directly related to the above operation description are omitted. First, an SBD signal is sent from the signal processing circuit 205 'to the printer controller 202 as a horizontal synchronization signal. This SBD signal is a signal obtained by delaying the BD signal from the printer engine 201 by a time corresponding to one cycle of the VCLK signal. Also, 8CLK having a frequency eight times the frequency of the VCLK signal is sent to the printer controller 202 as a clock signal. The 8CLK signal is stopped after the BD signal from the printer engine 201 is input until the SBD signal is output. This means that the transfer clock of the image data synchronized with the SBD signal inside the printer controller 202 is
After the SBD signal is input, the frequency is obtained by dividing the frequency of the first 8 CLK by 8. That is, the horizontal scanning synchronization timing is generated by the input / output control circuit 1 '.
In the input / output control circuit 1 ', VCL
By obtaining the K signal, the image data transfer clock inside the printer controller 201 and the VCL
The K signal is a clock signal having the same phase. Therefore, image data can be accurately transferred between the sending side and the receiving side without using the same clock.

Next, a control signal (hereinafter referred to as "DRC") input from the printer controller 202 to the signal processing circuit 205
T signal). This DRCT signal is a signal for specifying a state equivalent to the absence of the signal processing circuit 205. That is, when the DRCT signal is valid (L), the SVDO signal line carries the VIDEO signal from the printer controller 202, the SBD signal line carries the BD signal from the printer engine 201, and the 8CLK signal line oscillates. The CLK signal from the circuit 206 is output as it is. This mode is effective in the following cases, for example. V from printer controller 202
The IDEO signal is subjected to data conversion by a signal processing circuit 205 and converted into an SVDO signal.
By sending the signal to 1, the image data is delayed by three lines in the sub-scanning direction and by seven dots in the main scanning direction for data reference, as compared with the case where the signal processing circuit 205 'is not provided. Therefore, if printing is performed as it is by the conventional control system of the printer engine 201 and the printer controller 202, the image is shifted by 3 dots below the regular printing position and 7 dots to the right. The above problem can be solved by reducing the value of T1 in FIG. 4 by three lines and the value of T2 in FIG. 5 by seven dots on the printer controller 202 side. However, the printer controller 2
In the case where the above change cannot be easily made in 02 and the accuracy of the printing position is more important than the smoothness of the image, the DRCT signal may be made valid (L).

Other operations in the signal processing circuit 205 are performed in the same manner as in the first embodiment. However, in FIGS. 9 and 10, SVDO ', SBD' and 8CLK 'are signals which do not depend on the DRCT signal.

As described above, in the second embodiment, since the number of changes on the printer controller side is reduced, there are effects such as lower cost and shorter development period.

The present invention may be applied to a system constituted by a plurality of devices or to an apparatus constituted by a single device. It is needless to say that the present invention can be applied to a case where the present invention is achieved by supplying a program to a system or an apparatus. Furthermore, in the first and second embodiments described above, a laser beam printer has been described as an example. However, the present invention is not limited to this, and is applicable to a dot impact type, a thermal type, an ink jet type, and an electrostatic type. A printer of a recording type or a thermal transfer type may be used.

[0036]

As described above, according to the present invention,
Image data of the first printing density from the printer controller
Data for a plurality of lines in the storage means, and the stored image
Referring to the image data, the image data of the first print density is
Is to be converted into image data of the second printing density of the density.
Image data for printing from the printer controller
White data sent before is sent to storage means
By initializing the storage means by storing,
Image processing that can provide high-quality image output at low cost
An apparatus can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment in which an image processing apparatus according to the present invention is applied to a laser beam printer.

FIG. 2 is a block diagram showing a configuration of a signal processing circuit 205 according to the first embodiment.

FIG. 3 is a block diagram showing a configuration of a signal processing circuit 205 according to the first embodiment.

FIG. 4 is a timing chart showing a relationship between a synchronization signal and image data in the first embodiment.

FIG. 5 is a timing chart showing a relationship between a synchronization signal and image data in the first embodiment.

FIG. 6 is a timing chart illustrating the operation of the memory control circuit according to the first embodiment.

FIG. 7 is a diagram for comparing and explaining data before and after conversion of print density.

FIG. 8 is a diagram for comparing and explaining data before and after conversion of print density.

FIG. 9 is a block diagram illustrating a configuration example of a signal processing circuit according to a second embodiment.

FIG. 10 is a block diagram illustrating a configuration example of a signal processing circuit according to a second embodiment.

FIG. 11 is a timing chart illustrating an operation by a signal according to the second embodiment.

FIG. 12 is a circuit diagram showing a configuration of an input / output control circuit 1 'of the present embodiment.

FIG. 13 is a diagram schematically showing a conventional example.

FIG. 14 is a diagram showing a configuration of a conventional laser beam printer.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 I / O control circuit 2 SRAM 3 Address counter 4 Three-state latch 5 Memory control circuit 6-12 Shift register 13 Smoothing logic circuit 14 Parallel-serial conversion circuit 15 D flip-flop 51,63,64 NOT circuit 52-58 D flip-flop 59, 60 is a JK flip-flop 61 is a NAND circuit 62 is a 4-bit counter 65-67 selector circuit 62 4-bit counter 65-67 selector circuit 201 printer engine 202 printer controller 205 signal processing circuit 206 oscillation circuit

Continuation of the front page (72) Inventor Hiroshi Mano 3-30-2 Shimomaruko, Ota-ku, Tokyo Inside Canon Inc. (56) References JP-A-61-214666 (JP, A) JP-A-63-179748 ( JP, A) JP-A-63-208368 (JP, A) JP-A-64-1546 (JP, A) JP-A-1-244859 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , (DB name) B41J 2/44 H04N 1/23 103 H04N 1/387 101

Claims (1)

(57) [Claims] 1. An image sent from a printer controller.
In image processing devices that output images based on image data
To receive the synchronization signal sent from the printer controller
And after a lapse of a predetermined time from the synchronization signal.
Input means for inputting image data of a first print density, and a plurality of main scanning lines for inputting the image data input by the input means.
From the data stored in the storage means for storing the pixel of interest and
And the image data corresponding to the pixels surrounding the pixel
Reference means , corresponding to the pixel of interest based on a reference result of the reference means
Printing density of the obtained image data from the first printing density.
Conversion processing means for converting the data into high-density second print density data
And a step based on the image data converted by the conversion processing means.
Output means for outputting the image data of the first print density after receiving the synchronization signal.
During the predetermined time until it is sent, the printer
White data sent from the controller to the storage means.
By storing the information, a system for initializing the storage means is provided.
An image processing apparatus comprising: a control unit.