JPH07123185A - Picture processing unit - Google Patents

Abstract

PURPOSE:To allow the processing unit to be compatible with an interface among a picture input device, a picture output device and the picture processing unit whatever mode of the interface is set. CONSTITUTION:When the picture processing unit receives a synchronizing signal from a picture input device 15, a write clock for a FIFO 1 is generated from the received synchronizing signal. When the picture processing unit receives a synchronizing signal from a picture output device, a read clock for a FIFO 2 is generated from the received synchronizing signal. When a synchronizing signal is fed to the picture input device or the picture output device, the synchronizing signal generated in the inside of th picture processing unit 14 is supplied, When the synchronizing signal is supplied to both of the picture input device and the picture output device, the synchronizing signal generating parts of two systems are both started and the synchronizing signal generated by one is fed to the picture input device and the synchronizing signal generated in the other is fed to the picture output device respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention performs a predetermined process on image data input based on a main scanning synchronizing signal, a sub scanning synchronizing signal and a video clock to obtain a main scanning synchronizing signal,
The present invention relates to an image processing device that outputs based on a sub-scanning synchronization signal and a video clock.

[0002]

2. Description of the Related Art An image processing apparatus performs predetermined processing on image data input from a preceding apparatus and outputs the processed image data to a succeeding apparatus. FIG. 6 shows a digital copying machine as an example. As described above, the image processing device 14 includes the image input device 1
Input the image data from 5, and perform a predetermined process instructed by the image data, for example, an extraction process of extracting only an image of a predetermined region in the whole image, moving the position of the image of the predetermined region in the whole image The image data is output to the image output device 17 after being subjected to shift processing or the like.

The image input device 15 reads an image of a document by a scanner and generates digital image data, and the image output device 17 prints the image on a recording sheet.

In the prior art, as shown in FIG. 7, a main scanning synchronizing signal, a sub scanning synchronizing signal and a video clock are supplied from the image input device 15 together with the image data, and the image data is sent to the image output device 17. When outputting, a main scanning synchronizing signal, a sub scanning synchronizing signal and a video clock are generally supplied at the same time (for example, Japanese Patent Laid-Open No. 4-3).
No. 43568).

According to this structure, the image processing device 14 takes in the image data in synchronization with the main scanning synchronizing signal, the sub scanning synchronizing signal and the video clock supplied from the image input device 15. Then, when predetermined image processing is performed in synchronization with these synchronization signals and video clocks and the image data is output to the image output device 17, the main scanning synchronization signal, sub-scanning synchronization signal, and video clock are also supplied at the same time. .

[0006]

By the way, as for the mode of the interface between the image input device 15, the image output device 17, and the image processing device 14, that is, the main scanning synchronizing signal, the sub-scanning synchronizing signal, and the sending direction of the video clock, In addition to the one shown in FIG. 7, there is one shown in FIGS. 8A, 8B and 8C.

In FIG. 8A, the main scanning synchronizing signal, the sub scanning synchronizing signal, and the video clock are supplied from the image output device 17, but the image processing device 14 supplies the main scanning synchronizing signal and the sub scanning to the image input device 15. A case where a synchronizing signal and a video clock are supplied is shown. In this case, the image input processing in the image input device 15 is synchronized with the main scanning synchronizing signal, the sub scanning synchronizing signal, and the video clock supplied from the image processing device 14. Is done.

Further, FIG. 8B shows that the image processing device 14 includes
The case where the main scanning synchronization signal, the sub scanning synchronization signal, and the video clock are supplied from the image input device 15 and the main scanning synchronization signal, the sub scanning synchronization signal, and the video clock are also supplied from the image output device 17 is shown. In this case, the image output processing by the image output device 17 is performed in synchronization with the main scanning synchronization signal, the sub scanning synchronization signal, and the video clock supplied to the image processing device 14.

Further, FIG. 8C shows a case where a main scanning synchronizing signal, a sub scanning synchronizing signal, and a video clock are supplied from the image processing device 14 to both the image input device 15 and the image output device 17, respectively. In this case, the image input processing in the image input device 15 is performed in synchronization with the main scanning synchronization signal, the sub-scanning synchronization signal, and the video clock supplied from the image processing device 14, and similarly, the image output device 17 outputs the image. The output processing is performed in synchronization with the main scanning synchronizing signal, the sub scanning synchronizing signal, and the video clock supplied from the image processing device 14.

As described above, there are four types of interfaces between the image input device 15, the image output device 17, and the image processing device 14, but the conventional image processing device has a predetermined specific interface. There is a problem in that it is usually designed on the basis of the aspect, and therefore, it cannot correspond to other aspects of the interface.

The present invention solves the above-mentioned problems, and can cope with any type of interface between the image input device, the image output device and the image processing device. The purpose is to provide a device.

[0012]

In order to achieve the above object, an image processing apparatus according to claim 1 is an image processing apparatus for inputting and processing image data from an external device, which temporarily stores the image data. The image data is stored in the external device based on the memory means for storing it, the means for inputting the external synchronizing signal sent in synchronization with the image data from the external device, the means for generating the clock signal, and the information representing the configuration of the input image. Generating means for generating an internal synchronization signal for outputting from the clock signal, means for outputting the internal synchronization signal, means for instructing an operation mode, and an external synchronization signal and an internal signal in accordance with the instructed operation mode. Selecting means for selecting either one of the synchronizing signals and a write clock corresponding to the effective image area by using the selected synchronizing signal, and the input image data is stored in the memory. Means for writing the stage, characterized in that it comprises a means for sequentially reading out processing image data stored in said memory means.

An image processing apparatus according to a second aspect is an image processing apparatus for processing image data and outputting the image data to an external device, and memory means for temporarily storing the image data and output image data to the memory means. Based on the information indicating the configuration of the output image, a means for inputting an external synchronizing signal sent from an external device as a synchronizing signal for sending image data, a means for generating a clock signal, Generating means for generating an internal synchronization signal for synchronously outputting image data from the device, means for outputting the internal synchronization signal, means for instructing an operation mode, and an external synchronization signal in accordance with the instructed operation mode. Selecting means for selecting one of the internal sync signal and the internal sync signal, and a read clock corresponding to the effective image area is generated by using the selected sync signal. Characterized in that it comprises a means for outputting to an external device sequentially reads the image data stored in the unit.

An image processing apparatus according to a third aspect of the present invention is an image processing apparatus for inputting image data from a first external device, processing the input image data, and outputting the processed image data to a second external device. First memory means for temporarily storing image data, means for inputting a first external synchronization signal sent from a first external device in synchronization with the image data, means for generating a clock signal, and input image data A first internal synchronization signal for generating image data from a first external device is generated from the clock signal based on information indicating a configuration.
Generating means, means for outputting the first internal synchronization signal, means for instructing an operation mode, and one of a first external synchronization signal and a first internal synchronization signal depending on the instructed operation mode. A write clock corresponding to the effective image area is generated by using the first selecting means for selecting one and the synchronizing signal selected by the first selecting means, and the input image data is stored in the first memory means. Writing means and the first
Image processing means for sequentially reading and processing the image data stored in the memory means, generating an output image, second memory means for temporarily storing the image data, and the image processing means in the second memory means. Based on the information representing the configuration of the output image, means for sequentially writing the output images generated by the above, means for inputting the second external synchronization signal sent from the second external device as a synchronization signal for sending the image data, Second generation means for generating a second internal synchronization signal for synchronously outputting the image data from the clock signal, means for outputting the second internal synchronization signal, and the instructed operation. A second selecting means for selecting either the second external synchronizing signal or the second internal synchronizing signal according to the mode, and the effective image area using the synchronizing signal selected by the second selecting means. It generates a corresponding read clock, characterized in that it comprises a means for outputting the sequentially read data of the output image stored in the second memory means to the second external device.

[0015]

According to the present invention, it is possible to provide a versatile image processing apparatus, since it is possible to deal with any type of interface between the former apparatus, the latter apparatus and the image processing apparatus.

[0016]

Embodiments will be described below with reference to the drawings.
FIG. 1 is a diagram showing the configuration of an embodiment of an image processing apparatus according to the present invention. In the figure, the solid line shows the flow of image data, and the broken line shows the flow of signals other than image data, such as register parameter setting values, control signals, main scanning synchronization signals, sub-scanning synchronization signals, and video clocks.

In FIG. 1, the control device 20 centrally manages the operation of each part of the image processing device 14, and in the present invention, in particular, a register control signal is given to the register 5, Scan synchronization signal generator 10, 21
And a start signal is given to the main-scanning synchronization signal generators 11 and 22. Further, the control device 20 switches various signals input to the image processing device 14 and various signals output from the image processing device 14, as described below.

The register 5 has a parameter indicating an input image size, a parameter indicating an output image size,
Alternatively, it stores various parameters such as parameters for setting the connection mode of the interface mode. Here, the connection mode is set if the image input device 15 (not shown in FIG. 1) which is the former device and the image output device 17 (not shown in FIG. 1) which is the latter device are determined. , The control device 20 determines the connection mode when the image input device 15 and the image output device 17 are connected, and sets the connection mode in the register 5. Since the setting of the connection mode is made up of a 2-bit control signal, for example, in the case of the form of FIG.
0 "," 01 "in the case of FIG. 8A," 11 "in the case of FIG. 8B, and" 10 "in the case of FIG. 8C.

The image size parameter setting is
The controller 20 sets the number of clocks per main-scan synchronizing signal of the image input device 15 and the number of main-scan synchronizing signals per sub-scan synchronizing signal in the register 5 according to the specifications of the external device to be connected.

The FIFO 1 is provided to absorb the speed difference between the data transfer speed of the image input device 15 and the data transfer speed inside the image processing device 14 when the image data is input from the image input device 15. The FIFO 2 is provided to absorb the speed difference between the data transfer speed inside the image output device 17 and the image processing device 14 when the image data is output to the image output device 17.

The image processing unit 6 carries out an image extraction process for extracting data of only a specified region from the image data as effective data, and sets the bus width of the image data read from the FIFO 1 to that of the image processing unit 8 in the next stage. The processing for bus width conversion to match the bus width is performed.

The outline of the operation during the image extraction processing is as follows. Now, assuming that the user sets an extraction area 41 in the original 40 as shown in FIG. 2A, a main scanning extraction area signal 61 and a sub-scanning extraction area signal 62 are generated corresponding to the extraction area 41, The image processing unit 6 performs processing for extracting only the image in the extraction area 41 based on the main scanning extraction area signal 61 and the sub-scanning extraction area signal 62. 2A and 2B, 50 indicates a main scanning synchronization signal and 52 indicates a sub scanning synchronization signal.

The image processing unit 7 is provided to perform an image shift process in which the image data sent from the image processing unit 8 is shifted to a certain area within the page area and fitted. Further, the image processing unit 7 sets the bus width of the image data read from the image processing unit 8 to FIFO2.
It also performs a bus width conversion process that matches the bus width of.

The outline of the operation during the image shift processing is as follows. Now, the user is
As shown in, when a shift area 42 is set in the original 40, a main scanning shift area signal 51 and a sub scanning shift area signal 53 are generated corresponding to the shift area 42,
The image processing unit 7 performs shift processing to fit an image in the shift area 42 based on the main scanning shift area signal 51 and the sub-scanning shift area signal 53.

The image processing section 8 performs predetermined processing such as image data rotation processing and compression / expansion processing under the control of the control section 20.

The image control unit 3 generates a control signal necessary for performing the image extraction process and a control signal for causing the image processing unit 6 to perform the bus width conversion process.
Note that these control signals are generated based on the data size parameter supplied from the register 5.

The image control unit 4 generates a control signal required for performing the image shift process and a control signal required for causing the image processing unit 7 to perform the bus width conversion. Note that these control signals are generated based on the data size parameter supplied from the register 5.

The clock generator 12 generates a system clock having a predetermined frequency, and the system clock from the clock generator 12 is frequency-divided by the frequency dividing circuit 13 and output as a video clock. In this embodiment, the frequency dividing circuit 13 divides the system clock into 1/2.

The main scanning synchronizing signal generator 11 is based on the system clock supplied from the clock generator 12, and sets the main scanning parameter supplied from the register 5 and the main scanning synchronization supplied from the preceding and following devices. The main scanning synchronizing signal is generated according to the timing signal for signal generation.

Here, the operation of the main scanning synchronization signal generator 11 is well known, but its outline will be described with reference to the timing chart of FIG. 3A shows the case where the timing signal is not supplied, and FIG. 3B shows the case where the timing signal is supplied.

3A and 3B, the three types of signals of X, Y, and Z are signals that are generated inside the main scanning synchronization signal generation unit 11 and are used to generate the main scanning synchronization signal. .

The signal X changes from the high level to the low level when the system clock is counted by the number corresponding to the image size parameter in the main scanning direction given from the register 5, and becomes the high level again at the next rising edge of the system clock. Is.

When the signal Y is counted by the number corresponding to the period of the main scanning synchronizing signal given from the register 5, it becomes low level at every predetermined period and becomes high level again at the next rising edge of the system clock. However, this cycle is set to be slightly longer than the cycle of the main scanning synchronization signal. It should be noted that this signal Y always maintains a high level when a timing signal is supplied.

Further, the signal Z is the signal Y, as shown in FIG. 3A, when no timing signal is provided.
Goes to a low level at the falling edge of, and rises to a high level at the falling edge of the signal X. However, when the timing signal is supplied, as shown in FIG.
Rises to a high level at the falling edge of.

Then, the main scanning synchronization signal generation circuit 11
The main scanning synchronization signal is set to low level, that is, inactive at the fall of the system clock immediately after the signal Z becomes low level, and then the main scanning synchronization signal is made to fall at the fall of the system clock immediately after the signal X becomes low level. To a high level, that is, active.

The main scanning synchronizing signal is generated as described above.
The same applies to the main scanning synchronization signal generator 22. However, the main scanning synchronization signal generator 22 is activated by the controller 20 only in the case of the configurations shown in FIGS. 7 and 8C.

The sub-scanning synchronization signal generator 10 generates the sub-scanning synchronization signal based on the main-scanning synchronization signal supplied from the main-scanning synchronization signal generator 11 according to the parameter setting value for the sub-scanning supplied from the register 5. To generate. The operation in the case of generating the sub-scanning synchronization signal is well known and will not be described. The same applies to the sub-scanning synchronization signal generator 21. However, the sub-scanning synchronization signal generation unit 21 is activated by the control device 20 only in the case of the form shown in FIG. 8C.

The write clock synthesizing circuit 23 generates a write clock by taking the logical product of three kinds of signals, that is, a main scanning synchronizing signal, a sub scanning synchronizing signal and a video clock. This write clock is used when the FIFO 1 writes image data. In FIG. 1, the write clock synthesizing circuit 23 is shown as simply inputting three kinds of signals of the main scanning synchronizing signal, the sub scanning synchronizing signal, and the video clock, but in reality, FIG. 8A and FIG. 8C. In the case of the above form, the main scanning synchronization signal generated by the main scanning synchronization signal generation unit 11 (hereinafter referred to as an internal main scanning synchronization signal),
The sub-scanning synchronization signal generated by the sub-scanning synchronization signal generation unit 10 (hereinafter referred to as an internal sub-scanning synchronization signal) and the frequency dividing circuit 13
The video clock (hereinafter, referred to as an internal video clock) generated in (1) is input, and in the case of the configurations of FIGS. 7 and 8B, the main scanning synchronization signal (hereinafter, an external main clock) supplied from the image input device 15 is input. A scanning synchronization signal), a sub-scanning synchronization signal (hereinafter, referred to as an external sub-scanning synchronization signal), and a video clock (hereinafter, referred to as an external video clock) are input.

Therefore, specifically, the write clock synthesis circuit 23 has the configuration shown in FIG. In FIG. 4, the selector 30 selects and outputs one of the internal main scanning synchronization signal and the external main scanning synchronization signal, and which is selected is determined by the parameter of the connection mode given from the register 5. . The selector 31 selects and outputs either the internal sub-scanning synchronization signal or the external sub-scanning synchronization signal, and which one is selected is determined by the connection mode parameter given from the register 5. Similarly, the selector 32 selects and outputs either the internal video clock or the external video clock, and which one is selected is determined by the register 5.
The connection mode parameters given by

The outputs of the selectors 30, 31, 32 are logically ORed by the AND gate 33, and as a result, a write clock is generated and supplied to the FIFO1.

The read clock synthesizing circuit 24 generates a read clock by taking the logical product of three kinds of signals of the main scanning synchronizing signal, the sub scanning synchronizing signal and the video clock. This read clock is used when reading image data from the FIFO 2. In FIG. 1, the read clock synthesizing circuit 24 is shown as simply inputting three kinds of signals of the main scanning synchronizing signal, the sub scanning synchronizing signal, and the video clock, but actually, FIG. 7 and FIG. 8C. In the case of the above form, in order to generate the read clock, it is necessary to use the internal main scanning synchronization signal, the internal sub-scanning synchronization signal and the internal video clock, and FIGS. 8A and 8B.
In the case of the above form, since it is necessary to use the external main scanning synchronization signal, the external sub-scanning synchronization signal and the external video clock to generate the read clock, specifically, FIG.
The write clock synthesis circuit 23 shown in FIG.

The various components of the image processing apparatus 14 have been described above. Next, the process of writing the input image data will be described.

When the write clock is supplied, the FIFO 1 starts writing the input image data.
At this time, the FIFO 1 sequentially writes the image data at the rising edge of the write clock, and at the same time, the write address pointer is incremented. The empty flag of the FIFO1 is asserted (activated) when the image data is not written in the FIFO1, but is negated (deactivated) when the image data is written in the FIFO1.

The image controller 3 constantly monitors the empty flag of the FIFO 1 and, when the empty flag is negated, supplies a read clock, which is a control signal for reading the image data, to the FIFO 1. Image data is read from the FIFO 1 by this read clock.

In this way, the synchronization at the time of inputting the image data is performed. The read clock is also used to generate a synchronization signal used internally by the image controller 3.
That is, the read clock is used as the video clock of the synchronizing signal generated internally, and the main scanning synchronizing signal is generated based on the parameter in the main scanning direction supplied from the register 5, that is, the parameter for setting the number of pixels per line.

Here, the parameter for setting the number of pixels per line sets the number of video clocks during the period when the main scanning synchronizing signal supplied from the outside is active. That is, the image control unit 3 does not know the image size based on the number of video clocks during the period when the main scanning synchronization signal supplied from the outside is active, but sets the number of pixels per line set in the register 5. The number of pixels per line of the input image is known by the parameter.
Similarly, the sub-scanning synchronizing signal is generated based on the parameter in the sub-scanning direction supplied from the register 5, that is, the parameter for setting the number of lines per page.

Here, the parameter for setting the number of lines per page sets the number of pulses of the main scanning synchronizing signal during the period when the sub scanning synchronizing signal supplied from the outside is active. That is, the image control unit 3 does not know the image size based on the number of active main scanning synchronization signals during the period when the sub-scanning synchronization signal supplied from the outside is active, but does not know the image size, but one page set in the register 5 The number of lines per page of the image input by the parameter for setting the number of lines per is known.

Next, the operation in each connection mode will be described with reference to FIG. Note that FIG.
FIG. 5B is a timing chart showing timings of a write clock used when writing image data to FO1 and a read clock used when reading image data, and FIG. 5B shows a write clock used when writing image data to FIFO2. 6 is a timing chart showing the timing of a read clock used when reading image data.

First, the case of the form shown in FIG. 7 will be described. When copying is performed, first, the input image size is set by the operator or by detecting the document size by the document reading device. Based on this, the controller 20 sets the size of the read image data in the register 5. After that, the document reading operation is started, and the image input device 15 outputs the image data to the image processing device 14. At this time, the main scanning signal, the sub-scanning signal and the video clock are simultaneously output.

These sync signals are directly input to the image processing device 14, and the write clock synthesis circuit 23 generates a write clock. The image data input from the image input device 15 by this write clock are sequentially input to the input side F.
Written to IFO1. Note that the write control of the image data to the FIFO 1 does not depend on the above-described write clock, the video clock is directly input as the write clock, the main scanning synchronization signal and the sub-scanning synchronization signal are ANDed, and the result of the AND operation is calculated. It is needless to say that the same control can be performed by using the signal as the write enable signal of the FIFO 1, that is, the write enable signal, and is not limited to the control method described above.

Now, when data is written in the FIFO1, the empty flag of the FIFO1 becomes inactive, whereby a read clock which is a data read control signal from the FIFO1 is generated. The read clock is always generated when the empty flag of the FIFO 1 is inactive, so that the operation of reading the image data is continued. That is, since the image data is read by the read clock which is synchronized with the system clock inside the image processing apparatus 14, the synchronization can be achieved at the time of capturing the image. Further, since the FIFO 1 reads only the written amount, it is possible to take in the image data without excess or deficiency.

Here, when the captured image data is edited in a page, for example, when the extraction processing of the image data in pixel units or line units is performed in real time, it is necessary to know whether it is an extraction region, For that purpose, it is necessary to know the number of pixels from the start pixel and the number of lines from the start line of the currently input image data. Therefore, the image control unit 3 generates the first internal main scanning synchronization signal by counting the read clock. The first internal main scanning synchronization signal is a signal that is active during the period from the generation of the read clock until the count value matches the parameter indicating the image size in the main scanning direction. The counter for counting the read clock is reset when the count value matches the parameter indicating the image size in the main scanning direction.

The image control unit 3 also generates a first internal sub-scanning synchronization signal by counting the first internal main-scanning synchronization signal. This first internal sub-scanning synchronization signal is active during the period until the count value of the counter matches the parameter indicating the image size in the sub-scanning direction. The counter for counting the first internal main-scanning synchronization signal is reset when the count value matches the parameter indicating the image size in the sub-scanning direction.

By the way, depending on the count value of the counter that counts the read clock and the count value of the counter that counts the first internal main-scanning synchronization signal, the number of pixels from the start pixel of the currently input image data, the start line It is possible to know from what line the data is. Therefore, the image control unit 3 discriminates the extraction region from these count values and causes the image processing unit 6 to execute the extraction process.

Next, reading of image data from the FIFO 2 will be described. When performing copying, the size of the output paper is set together with the setting of the input image size. Based on this, the control device 20 sets the size of the output image data in the register 5.

The image control unit 4 monitors the full flag indicating the presence / absence of a free area in the FIFO 2, and if the full flag is inactive, generates a write clock which is a control signal for writing data to the FIFO 2. Here, when the image data to be output is edited in a page, for example, when performing image shift processing in pixel units or line units of the image data in real time, it is necessary to know whether it is an effective image area. It is necessary to know at what number of pixels the data written in the FIFO 2 is from the leading pixel and at what line from the leading line. This is because it is necessary to write white data in an area other than the effective image area.

Therefore, the image control unit 4 counts the write clock to generate the second internal main scanning synchronization signal. This signal is active during the period from the generation of the write clock until the count value matches the parameter indicating the image size in the main scanning direction. The first internal main signal generated by the image control unit 3 described above. This signal is different from the scan synchronization signal. The counter for counting the read clock is reset when the count value matches the parameter indicating the image size in the main scanning direction.

The image control unit 4 also generates a second internal sub-scanning synchronization signal by counting the second internal main-scanning synchronization signal. The second internal sub-scanning synchronization signal is active during the period until the count value of the counter matches the parameter indicating the image size in the sub-scanning direction. The counter for counting the second internal main-scanning synchronization signal is reset when the count value matches the parameter indicating the image size in the sub-scanning direction.

By the way, the current FI is determined by the count value of the counter that counts the read clock and the count value of the counter that counts the second internal main scanning synchronization signal.
It is possible to know the number of pixels from the head pixel of the image data written in the FO2 and the number of lines of the address from the head line. Therefore, the image control unit 4
The shift area is discriminated from these count values, and the image processing section 7 is caused to execute the shift processing for operating the address. Then, the image data that has been subjected to the shift processing is sequentially written in the FIFO2.

In this embodiment, since the value of the connection mode parameter is "00", the main scanning synchronization signal generation section 11 and the sub-scanning synchronization signal generation section 10 are activated by the control device 20, and by the above-mentioned operation, A main scanning synchronization signal and a sub scanning synchronization signal are generated respectively. In this case, the image size of the signal X in FIG. 3 in the main scanning direction naturally becomes the size of the output image.

Then, the internal main-scanning synchronizing signal, the internal sub-scanning synchronizing signal and the internal video clock are supplied to the image output device 17 and also to the read clock synthesizing circuit 24 to be used for generating the read clock.

Image data is read from the FIFO 2 by this read clock and output to the image output device 17. It should be noted that the read control of the image data of the FIFO2 does not depend on this read clock, but a video clock is directly supplied to the FIFO2 as a read clock to obtain the logical product of the main scanning synchronization signal and the sub-scanning synchronization signal and obtain the signal of the logical product Needless to say, the same control can be performed by using the read enable signal of the FIFO 2, that is, the read enable signal, and is not limited to the control method described above.

Next, the case of the form shown in FIG. 8A will be described. In this case, since the connection mode parameter value is “01”, the main-scanning synchronization signal generation unit 11 and the sub-scanning synchronization signal generation unit 10 are activated, and the main-scanning synchronization is generated based on the setting of the input image size. A signal generator and a sub-scanning synchronization signal generator are generated. These synchronizing signals are supplied to the image input device 15 together with the internal video clock from the frequency dividing circuit 13, and the image input device 15 performs image input processing based on these signals.

Further, the write clock synthesis circuit 23 generates a write clock using the internal main scanning synchronization signal, the internal sub-scanning synchronization signal and the internal video clock to generate the FIFO1.
Supply to. However, the read clock synthesis circuit 24
An external main scanning synchronization signal supplied from the image output device 17,
A read clock is generated using the external sub-scanning synchronization signal and the external video clock and is supplied to the FIFO 2. The other operations are the same as those described above, and the description thereof will be omitted.

Next, the case of the form shown in FIG. 8B will be described. In this case, the parameter value of the connection mode is "11", so the main scanning synchronization signal generation unit 11 and the sub-scanning synchronization signal generation unit 10 are not activated. Therefore, the write clock synthesis circuit 23 generates a write clock using the external main scanning synchronization signal, the external sub-scanning synchronization signal, and the external video clock supplied from the image input device 15, and then the FI.
Supply to FO1. In addition, the read clock synthesis circuit 24
Generates a read clock using the external main scanning synchronization signal, the external sub-scanning synchronization signal, and the external video clock supplied from the image output device 17, and supplies the read clock to the FIFO 2. The other operations are the same as those described above, and the description thereof will be omitted.

Next, the case of the form shown in FIG. 8C will be described. In this case, the connection mode parameter value is “10”, so that not only the main scanning synchronization signal generation unit 11 and the sub scanning synchronization signal generation unit 10 are activated, but also the main scanning synchronization signal generation unit 22 and the sub scanning synchronization signal generation unit 22. The scan synchronization signal generator 21 is also activated. Then, the main scanning synchronization signal generated by the main scanning synchronization signal generation unit 11 and the sub-scanning synchronization signal generated by the sub-scanning synchronization signal generation unit 10 together with the internal video clock generated by the frequency dividing circuit 13 are input to the image input device 15. Is supplied to
The main scanning synchronization signal generated by the main scanning synchronization signal generation unit 22 and the sub scanning synchronization signal generated by the sub scanning synchronization signal generation unit 21 are supplied to the image output device 17 together with the internal video clock generated by the frequency dividing circuit 13. To be done.

As a result, in the image input device 15, the main scanning synchronization signal generated by the main scanning synchronization signal generating section 11,
An image input process is performed based on the sub-scanning synchronization signal generated by the sub-scanning synchronization signal generation unit 10 and the internal video clock generated by the frequency dividing circuit 13. In the image output device 17, the main scanning synchronization signal generation unit is performed. An image output process is performed based on the main-scanning synchronization signal generated at 22, the sub-scanning synchronization signal generated at the sub-scanning synchronization signal generation unit 21, and the internal video clock generated at the frequency dividing circuit 13.

Further, the write clock synthesis circuit 23 generates a write clock using the first internal main-scan synchronizing signal, the first internal sub-scan synchronizing signal and the internal video clock and supplies the write clock to the FIFO 1 to synthesize the read clock. Circuit 24
Generates a write clock using the second internal main scanning sync signal, the second internal sub-scan sync signal, and the internal video clock, and supplies the write clock to the FIFO2.

The internal main scanning synchronization signal here may be the main scanning synchronization signal generated by the main scanning synchronization signal generator 11. This is because the main scanning synchronization signal generated by the main scanning synchronization signal generation unit 11 and the main scanning synchronization signal generated by the main scanning synchronization signal generation unit 22 are synchronized.
The other operations are the same as those described above, and the description thereof will be omitted.

In the above embodiment, the image processing device 14
A bidirectional gate is provided in each of the interface units that connect the image input device 15 and the image output device 17, and the direction of the gate is switched by the control device 20 according to the connection mode, so that the external interface line can be used as it is. It is clear that you can do it. Further, the connectors for the internal synchronizing signal and the external synchronizing signal may be provided separately and separately.

Although one embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and various modifications can be made. For example, in the above-described embodiment, the image processing device 14 includes the control device 20, but it may be controlled by an external device control device.

[0072]

As is apparent from the above description, according to the present invention, it is possible to deal with any aspect of the interface with the device of the preceding stage and the device of the subsequent stage, so that various synchronizations can be performed. The connection restriction due to the signal transmission direction is eliminated, and this makes it possible to provide versatility as an image processing apparatus.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a diagram illustrating image extraction processing and image shift processing.

FIG. 3 is a diagram for explaining generation of a main scanning synchronization signal.

FIG. 4 is a diagram showing a specific configuration example of a write clock synthesis circuit 23.

FIG. 5 is a timing chart showing timings of read clocks and write clocks of FIFO1 and FIFO2.

FIG. 6 is a diagram showing a schematic configuration of a digital copying machine.

FIG. 7 is a diagram illustrating an aspect of an interface between an image input device, an image output device, and an image processing device.

FIG. 8 is a diagram showing another aspect of the interfaces of the image input device, the image output device, and the image processing device.

[Explanation of symbols]

1, 2 ... FIFO, 3, 4 ... Image control unit, 5 ... Register, 6, 7, 8 ... Image processing unit, 10, 21 ... Sub-scanning synchronization signal generation unit, 11, 22 ... Main scanning synchronization signal generation unit, 12
... clock generator, 13 ... frequency dividing circuit, 14 ... image processing device, 15 ... image input device, 17 ... image output device,
20 ... Control device, 23 ... Write clock synthesis circuit, 24
… Read clock synthesis circuit.

Claims (3)

[Claims] 1. An image processing apparatus for inputting and processing image data from an external device, wherein a memory means for temporarily storing the image data and an external synchronization signal sent from the external device in synchronization with the image data are input. Means, a means for generating a clock signal, a generation means for generating an internal synchronization signal for outputting image data to an external device from the clock signal based on information representing the configuration of an input image, the internal synchronization signal Output means, an operation mode instructing means, a selecting means for selecting one of an external synchronizing signal and an internal synchronizing signal in accordance with the instructed operating mode, and an effective image using the selected synchronizing signal. A unit that generates a write clock corresponding to the area and writes the input image data in the memory unit, and sequentially reads the image data stored in the memory unit. The image processing apparatus characterized by comprising means for the processing. 2. An image processing apparatus for processing image data and outputting it to an external device, said memory means for temporarily storing the image data, means for writing the output image data in this memory means, and for sending the image data. Means for inputting an external synchronizing signal sent from an external device as a synchronizing signal of, a means for generating a clock signal, and a means for synchronously outputting image data from the clock signal based on the information indicating the configuration of the output image Generating means for generating an internal synchronization signal, means for outputting the internal synchronization signal, means for instructing an operation mode, and selection of either an external synchronization signal or an internal synchronization signal according to the instructed operation mode Selecting means for generating a read clock corresponding to the effective image area by using the selected synchronizing signal, and the image data stored in the memory means is generated. The image processing apparatus characterized by comprising means for outputting the next read to an external device. 3. Inputting image data from a first external device,
An image processing apparatus for processing input image data and outputting the image data to a second external device, the first memory means for temporarily storing the image data, and the image data sent from the first external device in synchronization with the image data. First
A means for inputting an external synchronization signal, a means for generating a clock signal, and a first internal synchronization signal for causing the first external device to output image data based on the information representing the configuration of the input image. First generation means for generating from a clock signal, means for outputting the first internal synchronization signal, means for instructing an operation mode, first external synchronization signal and a first operation signal according to the instructed operation mode First selecting means for selecting either one of the internal synchronizing signals, and a write clock corresponding to the effective image area is generated by using the synchronizing signal selected by the first selecting means, and input image data is generated. A unit for writing in the first memory unit, an image processing unit for sequentially reading and processing the image data stored in the first memory unit, and generating an output image, and temporarily storing the image data. Second memory means, means for sequentially writing output images generated by the image processing means in the second memory means, and second external device sent as a synchronization signal for sending image data from a second external device. Means for inputting a synchronizing signal; second generating means for generating a second internal synchronizing signal for synchronizing and outputting the image data from the clock signal based on information indicating the configuration of the output image; Means for outputting a second internal synchronization signal; second selection means for selecting one of the second external synchronization signal and the second internal synchronization signal according to the instructed operation mode; A read clock corresponding to the effective image area is generated by using the synchronization signal selected by the second selection means, and the data of the output image stored in the second memory means is sequentially read out to obtain a second external device. An image processing apparatus comprising: