JP2502753B2 - Image output device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image output device having an image memory for expanding and outputting bitmap data.

2. Description of the Related Art A conventional image output device will be described by taking a laser printer as an example, which is common among image output devices. FIG. 7 is a block diagram of a conventional laser printer. As shown here, the laser printer includes an interface unit 2, a video data processing unit 3, a laser scan unit unit 4 (hereinafter referred to as LSU).
It is abbreviated as part. ) Engine control means 5 Engine mechanical section 6
It is composed of 5 blocks.

The outline of the laser printer having this configuration will be described below. The laser printer connected to the host computer 1 receives the text data sent from the host computer 1 via the interface means 2 and stores it in the memory in the video data processing means 3. Next, this text data is expanded into bit map data which is image data in the video data processing means 3 and is an output device.
In synchronization with a horizontal synchronizing signal (hereinafter abbreviated as HSYNC) sent from the LSU unit 4, the video data (hereinafter abbreviated as VDOUT) that is a serial output is sent to the LSU unit. In addition, the video data processing means 3 manages the engine control means 5 that controls the engine mechanical section 6 such as paper feed and main motor drive in accordance with the output of VDOUT. In this way, the image formation of the image data is performed.

FIG. 8 shows a block diagram of a video data processing unit, which is a conventional structure of the video data processing means 3 in the laser printer configured as described above. Where 7 is MPU,
Reference numeral 8 denotes a DRAM block section having DRAM, and 9 denotes a VRAM block section. 10 is an address decoding means,
The address bus (MPUA) of the MPU7 is input and the address is decoded to identify which memory of the DRAM block unit 8 and the VRAM block unit 9 the MPU7 is requesting access to, and the DRAM arbitration means 12 to be described later. On the other hand, an accelerator request signal (DRAMRQ) with DRAM, or VR for the VRAM arbitration means 16 described later.
Generates access request signal (VRAMRQ) with AM9. 1
Reference numerals 1 and 15 are refresh means for the DRAM block unit 8 and the VRAM block unit 9, respectively.
This is a means for requesting refresh of the VRAM block unit 9. The refresh means 11 generates a refresh request signal (DREFRQ) to the DRAM arbitration means 12 described later, and the refresh means 15 generates a refresh request signal (VREFRQ) to the VRAM arbitration means 16 described later. 12 and 16 are respectively
The DRAM arbitration unit 12 is an arbitration unit for the DRAM block unit 8 and the VRAM block unit 9, and the DRAM arbitration unit 12 arbitrates the access request signal DRAMRQ and the refresh request signal DREFRQ and indicates which arbitration is performed with respect to the DRAM timing unit 13 described later. DRAM
The VRAM arbitration means 16 uses the start command signal group (DSTCOM) to arbitrate the access request signal VRAMRQ and the refresh request signal VREFRQ and indicates the state of arbitration with respect to the VRAM timing means 17, which will be described later (VSTC).
OM) to send. 14 is the address bus MPUA as input
The bank switching means sends a bank switching state signal group (BANKST) to the AM timing means 13. Since the user area for storing the text data in the DRAM block section 8 is fixed for bank switching, it is necessary to expand the memory according to the amount of text data of the user so as not to cause a memory overflow. , Used when expanding this DRAM. A DRAM timing signal 13 is a signal group DSTCOM sent from the DRAM arbitration means 12.
Generates a timing signal group (DRAMT) for DRAM access to the DRAM block section 8 and inputs a signal group BANKST sent from the bank switching means 14.
A bank information signal (BANKO) is sent to the DRAM block section 8. Although not shown in FIG. 8, the bank information signal BA
Bank information signal B as in DRAM block 8 for NKO
It is assumed that there are extended DRAM block parts for ANK1 and BANK2. In this way, the DRAM block section 8 has an address MPUA, a bank information signal BANKO, and a timing signal group D.
The RAMT and data bus MPU D are connected to enable access from MPU7 to DRAM. Reference numeral 17 denotes VRAM timing means, which inputs the signal group VSTCOM sent from the VRAM arbitration means 16.
A timing signal group (VRAMT) for VRAM access is sent to the VRAM block unit 9. VRAM block 9 is address bus M
It is connected to the PUA and the data bus MPUD, inputs the signal group VRAMT, and outputs video data (VD
The video data, which is a serial output, is sent to the video signal synchronizing means 18 in synchronization with the clock sent through B). As described above, the data bus VDB is composed of the clock line, the serial data line, and the serial data line. here
Since the capacity of the memory buffer of the VRAM block section 9 is generally limited, when the sequential read speed of the synchronization signal HSYNC is faster than the speed of developing the image data to this memory buffer, the transfer of the data before the image data is expanded. An error condition (hereinafter, this error condition is referred to as overrun) will occur. To expand this overrun limit, it is necessary to expand the memory buffer of the VRAM block unit 9. Reference numeral 18 denotes a video signal synchronizing means, which is a synchronizing signal H sent from an LSU section (not shown).
Synchronize with SYNC, count the blanking time, generate a clock to the VRAM block unit 9 so as to output the video data sent from the VRAM block unit 9 to the effective print area, and output it to the LSU as the serial video data output VDOUT. to be sending. Further, the MPU 7 detects the synchronizing signal HSYNC, counts the number of rasters of output data, and controls and manages the VRAM block unit 9 and the video signal synchronizing means 18.

As described above, the system and user areas are divided into the DRAM block section 8 and the image data is expanded independently on the VRAM block section 9. Since the VRAM block section 9 has a dual port, access from the MPU 7 is made. The configuration is easy to control, such as easy access by the clock from the video signal synchronizing means 18.

On the other hand, an expansion board for expanding the memory area is required separately for the DRAM block section 8 and the VRAM block section 9, and the system configuration is not convenient for the user.

FIG. 9 shows characters developed as bitmap data which is image data of an image. As an example, the expansion of the characters A and B will be described. Here, for ease of explanation, each character is composed of 25 × 25 dots, 1 dot is considered as 1 bit unit, 1 dot painted black is 1 and empty dot is 0. Some 25 in the font
Each bit information of x25 is stored with a code of 1 or 0. DR
The text data stored in AM is expanded as bitmap data to the VRAM buffer while referring to the character font via the MPU. In general, this expansion sequentially expands each character and writes it in the buffer. Ninth
In the figure, the character "A" is first bit-mapped in the VRAM buffer and each bit is written according to the code of the character font. Next, the bit map expansion of the character "B" is performed. Here, when the character "A" and the character "B" overlap, the normal writing operation is performed, and the character "B" is written. At the time of performing the plug-in operation, the 25 × 25 bits are written with the information of the character “B”, and the character “A” is partially erased. In order to prevent this, after the character "A" is expanded, the logical sum of the character "A" and the character "B" is performed in bit units, and the overlapped information as shown in FIG. Can write This function is hereinafter referred to as overwriting. In general, VRAM has this overwriting function, and VRAMs to be discussed later are treated as having this function.

Next, the control performed by the MPU 7 of FIG. 9 will be described using the flowchart of FIG. Here, the HSYNC interrupt routine generates an interrupt to the MPU 7 each time a pulse is input to HSYNC. The flowchart will be described below. First, in the main routine, in step (a), variables X and Y are initialized. Here, X is a raster number written by the MPU 7 in the VRAM area, and Y is a counter number indicating the number of interrupts for each HSYNC. In step (b), N is set to the number of rasters to be printed. In step (c), the HSYNC interrupt is enabled. In step (d), the blanking time or the like is set for the video signal synchronizing means 18 to activate it. In step (e), the magnitude of X and Y is compared to determine whether or not there is an empty raster for writing the bitmap data in the VRAM block section 9. If there is no empty raster, return to step (e), and if there is an empty raster, go to step (f). In step (f), the bitmap data for one raster is written in the VRAM block unit 9 and the value of X is incremented by +1. HS in step (g)
It is determined whether the YNC counter number Y is equal to the raster number N to be printed, and if X = Y, go to step (h). In step (h), the video signal synchronizing means 18 is stopped and the writing of the bitmap data to the VRAM block section 9 is completed. Next, in the HSYNC interrupt routine, in step (i), the value of the output raster number Y is incremented by +1. In step (j), Y and N are compared to determine whether printing is completed. If Y = N, go to step (k) and Y ≠
If N, the process ends. In step (k), the HSYNC interrupt is prohibited.

However, in this case, since the DRAM block part and the VRAM block part are divided into different blocks, the DRAM block part and the VRAM block part are prevented in order to prevent overflow of user data and overrun of the VRAM block part. It was necessary to add blocks and blocks, which required much cost and labor.

Means for Solving the Problem In order to solve this problem, the present invention is an image output device that bit-expands image data to be printed sent from the outside and outputs the data to be printed from the outside. A processing unit for expanding the map, a storage unit for storing data to be bit-developed by the processing unit and an image storage region for storing image data bit-developed by the processing unit in the same address space; It comprises an access means for accessing and sequentially outputting an image storage area in the means, and an arbitration means for preventing simultaneous access of the processing means and the access means.

With this configuration, even if the DRAM block section and the VRAM block section are provided in the same address space, simultaneous access is blocked by the arbitration means, so that even if they are provided in the same address space, data destruction can be avoided.

Embodiment Hereinafter, an image output apparatus according to an embodiment of the present invention will be described.

First, FIG. 1 is a block diagram showing the configuration of the present embodiment. Here, 30 is a microprocessor unit (hereinafter referred to as MPU) for controlling the image output apparatus, and 31 is a DRA.
Bank switching means for deciding which DRAM block part to access when there are a plurality of M block parts 42,
32 is an address conversion unit for converting the value of the address bus MPUA output from the MPU 30, 33 is an address decoding unit, and 34 is a video band buffer (hereinafter referred to as VBB) which is a part of the storage area of the DRAM block unit 42. VBB mode switching means for switching the storage capacity, 35 video data generating means (hereinafter referred to as VDG) for outputting the video data output signal VDOUT, 36 DRAM address generating means for outputting to the DRAM block section 42 Address bus DRA
Generate M. 37 is a refresh means for DRAM, D
The DRAM access request signal REFREQ is output at the cycle of the RAM refresh cycle time. A DRAM arbitration unit 38 is a unit that arbitrates a plurality of access request signals to the DRAM block unit 42 and permits access to only one access request. 39 is DRAM timing means, DRAM
Timing signal group DRAM for accessing the block part
It is a means for outputting the T output and the bank signals BANKO, BANK1, BANK2. Reference numeral 40 is a bus switching means for switching whether or not the data bus MPU D of the MPU is electrically connected.
Reference numeral 41 is an overwriting pattern generating means, and the overwriting is the function described above. 42 is a DRAM block section.

The operation of the configuration of the video data processing block of the image output apparatus of the present embodiment configured as described above will be described below. First, an outline of data processing in this video data processing block configuration will be described. Since the data to be printed from the outside is stored in the user data area which is a part of the DRAM block unit 42, this data is expanded into bitmap data by the MPU 30. At this time, when font data is required, processing such as referring to a font memory (not shown) is involved. The bitmap data is stored again in the VBB area which is a part of the DRAM block unit 42. Book VBB
The data stored in the area is read using the VDG 35, this data is converted to serial data, synchronized with the HSYNC signal, and transmitted to the above-mentioned LSU. A configuration for performing the above data processing will be described below.

The access request in the DRAM block unit 42 has four modes in total. The first is an access request from the MPU to the VBB area. The second is an access request from the MPU to areas other than the VBB area. The third is a request for VDG35 to access the VBB area. Fourth is the DR of the DRAM block section 42
It is a refresh access request for refreshing to hold the data on AM. As described above, there are four modes for accessing the DRAM block section 42, and at least 2
Modes, and when there are many modes, three modes simultaneously issue access requests, so some kind of arbitration is required. The means for taking these arbitrations is the DRAM arbitration means shown in 38, and the access request signal VBBRQ from the MPU to the VBB area, the access request signal MPURQ from the MPU to areas other than the VBB area, and the access request from the refresh means 37. Input 4 signals of signal REFRQ,
Arbitration is performed internally, one access request signal is permitted, and the start command signal group STCOM is output to inform the DRAM timing means 39 which access request is to be executed. The DRAM timing means 39 inputs the output signal BANKST of the bank switching means 31 for bank switching necessary when there are a plurality of the above-mentioned signal group STCOM and DRAM block section 42, and is necessary for DRAM access by this means. The bank switching signals BAN0, BANK1, BANK2 are generated together with the generation of the timing signal group DRAMT. Also
The DRAM address generating means 36 informs the DRAM timing means 39 which access request is executed by the DRAM arbitration means 38,
Which address bus should be sent to the DRAM block unit 42 is determined according to the timing. Therefore, when the address switching control output signal group DAGCOM of the DRAM timing means 39 is input to the DRAM address generating means 36, the DRAM address generating means 36 follows the VBB address bus VBBA, MPU address bus MPUA, VDG address bus according to this signal group DAGCOM. VD
It has a function of selecting one of the GAs and connecting it to the address bus DRAMA for sending to the DRAM block section 42.

Next, the operation of overwriting in the VBB area will be described. Although the overwriting in the VBB area is required as described in the conventional example, the DRAM block unit 42 in the present invention does not have the additional function of the VRAM in the conventional example, and therefore an additional overwriting means is required. First, since the write data is sent from the MPU 30 to the VBB area through the data bus MPUD, this data is input to the A section of the overwriting pattern generating means 41. On the other hand, from the DRAM timing signal 39, the DRAM block
The read timing to 42 is executed and the data in the VBB area is input to the B section of the overwriting pattern generating means 41 through the DRAM data bus DRAMD. The input data to the section B is latched by the output signal OVC of the DRAM timing means 39, the data inputted to the section A is superposed and the data is written to the final VBB area as the data bus D.
Output to RAMD. In this way, the data in the VBB area is read, the data sent from the MPU 30 is superimposed, and the result is written in the VBB area. Such a method is called read-modify-write and is hereinafter referred to as RMW. As described above, the MPU30 can recognize that there is only one write cycle in the VBB area, but the actual hardware automatically creates the RMW cycle. These cycles are DRAM timing means 39
Are all made in.

Next, the VBB mode switching means 34 will be described. VBB
The area will be described in detail later, but when the memory capacity of the VBB area is made variable, or when it is expanded to a plurality of DRAM block parts to increase the memory capacity of the DRAM block part 42, VB
Location of B area needs to be changed. Now suppose that the memory capacity of the VBB area is changed. At this time, the memory capacity information is input from the MPU 30 to the VBB mode switching means 34 via the data bus MPUD. The VBB mode switching means 34 outputs memory capacity information to each means via the VBB data bus VBBD, that is, VDG 35, address conversion means 32,
Send to. VDG35 inputs the above memory capacity information,
The signal pattern generated on the VDG address bus VDGA is switched according to the memory capacity information. Also, as will be described later, the VBB area uses the ring buffer method, so the actual MP
Since it is necessary to convert the address information output from U into physical address information on VBB, it is necessary to switch the address conversion means 32 according to the memory capacity information. The bank switching means 31 is a means used when changing the location of the VBB area.

Next, the VDG35 will be described in more detail. Figure 2 shows V
It is an internal block diagram of DG35. Reference numeral 44 is a timing control means for synchronizing the internal timing of the VDG 35 with the external cycle signal HSYNC. Reference numeral 45 is an address generation counter means, which is a counter that counts up by +1 and uses its output as an address bus for accessing the VBB area. Reference numeral 46 is a VBB memory capacity selection means, which is means for inputting memory capacity information of the VBB area from the VBB bus VBBD, converting it into an address for actually accessing the VBB area, and outputting it to the VDG address bus VDGA. . Reference numeral 47 is a data latching means, which is means for latching the data in the VBB area because it is inputted via the DRAM data bus DRAMD. Reference numeral 48 is a parallel-serial conversion means for transferring data in the VBB area to the data bus V
It is input via DQ, this data is converted from parallel data to serial data, and is sent to the above-mentioned LSU as a video data output signal VDOUT. Reference numeral 49 is a VDG control means, which has a function of counting the number of pulses of the external synchronization signal HSYNC and transmitting it to the MPU30 via the MPU data bus MPUD in order to know up to which raster the video data output signal VDOUT has been transmitted. . In addition, input the number of rasters to output the video data output signal VDOUT from MPU30 via MPUD, and when the output data is sent from VDOUT to the raster specified by MPU30, VDG35 will stop automatically. It has a function of sending the signal STOP to the timing control means 44. It also has a start function via a start signal.

Next, the operation of the internal block of VDG35 will be described. Timing control means 4 that synchronizes the clock synchronized with the external synchronization signal HSYNC
Signals generated by 4 and dividing this clock PSCLK, LD, VD
Make GRQ. VDGRQ is a request signal sent to the DRAM arbitration means 38 to access the VBB area from the VDG 35, and when the DRAM arbitration means 38 permits, the data of the VBB area indicated by the address of the address bus VDGA output from the VDG 35. Read into VDG35. On the other hand, the address generation counter means 45 increments the counter by +1 by inputting the output signal ACLK of the timing control means 44, and this output is increased by VBB memory capacity selection means 4 via the bus Q.
Send to 6. The VBB memory capacity selecting means 46 processes the data from the bus Q according to the memory capacity of the VBB area input from the VBB bus VBBD, and outputs it as actual address information to the VDGA. Explaining what kind of processing is done here, for example, when the memory capacity is small, the upper bits of the data from the bus Q are deleted, and only the number of bits matching the actual address space is output to the VDG address bus VDGA. Means The data in the VBB area indicated by the address thus output is latched in the data latch means 47 via the DRAM data bus DRAMD. This parallel data is converted into serial data through the parallel-serial conversion means 48 and sent out from VDGOUT as a video data output signal.
The signal flow of the video data processing unit has been described above with reference to FIGS. 1 and 2.

Next, the VBB area will be explained. FIG. 3 shows a memory map of the DRAM block unit 42. Reference numeral 50 denotes an actual memory space of the DRAM block unit 42. 51 is the area used by the system, 52
Is a user data area for storing data sent by the user to the image forming apparatus, and 53 is a VBB area. 54 is MPU
It is the virtual memory space of the VBB area viewed from 30. Virtual memory space in the memory mapped as above
Reference numeral 54 is a place for storing the data developed in the bitmap for one page of the printing paper output from the image forming apparatus. Now the MPU 30 has addresses A to B in the virtual memory space 54.
When the bit map data is sequentially written into, the addresses are actually written in order from the addresses a to b of the VBB area 53 of the real memory space 50. This data is read in order from address a to b through VDG35 and converted to serial data.
Sent to LSU. Next, the address c of the virtual memory space 54
Similarly, the data written in the addresses a to d are actually written in the addresses a to b of the VBB area. As described above, the VBB area 53 has a ring buffer structure. Therefore, the data in the VBB area 53 is sequentially read from the addresses a to b, a to b ...
Sent to U. Also, when the bitmap data is written from the MPU 30 to the virtual memory space 54 at the addresses A to B, C to D, ..., Actually, the addresses a to b to the VBB rear 53,
Written as a to b.

Next, the control performed by the MPU 30 in this embodiment will be described using the flowchart in FIG. Here, the HSYNC interrupt routine is executed by the external synchronization signal HSYN of FIG. 1 in terms of hardware.
By inputting C to the interrupt terminal of MPU30, HSYNC
Each time a pulse is input to, an interrupt is generated in MPU30. This means that an interrupt occurs every raster. The flowchart will be described below. First, in the main routine, variables X and Y are initialized in step (a). X is a raster number written in the VBB area by the MPU 30, and Y is a counter number indicating the number of interrupts for each HSYNC. The number of rasters N to be printed in step (B) N
To VDG. In step (c), enable HSYNC interrupt and activate VDG. V in step (d)
Judgment is made by referring to X and Y in order to check whether or not there is an empty raster for writing bitmap data in BB. If there is no empty raster, return to step (d), and if there is, move to step (e). In step (e), one raster of bitmap data is written to VBB, and 1 is added to the value of X. In step (f), it is judged whether the number of HSYNC counters is equal to the number of rasters to be printed, and if X
When ≠ Y, the process returns to step (d), and when X = Y, the writing of the bitmap data to VBB is completed. Then HS
The YNC counter number is read from VDG and stored in Y. Step (h) is Y to judge whether printing is completed.
Is compared with N, and if Y = N, the process proceeds to step (i), and if Y ≠ N, the process ends. Disable the HSYNC interrupt in step (i). The operation of the block configuration of the video data processing unit shown in FIG. 1 has been described above with reference to FIGS. 2, 3 and 4.

Next, the case where the VBB area is made variable will be described with reference to FIG. When the VBB area is 64 KB, the addresses of the virtual memory space corresponding to the addresses FFFFF (H) to F0000 (H) in the real memory space are 0 to FFFF (H) for bank 1 and 10000 (H) to 1FFFF (H for bank 2). ), Bank 3 is 2000
Since it changes from 0 (H) to 2FFFF (H) ..., it can be easily converted to an address in the real memory space by ignoring the upper address bits of the virtual memory space and validating only the lower 4 digits of the hexadecimal number. Next, when the VBB area is 48 KB, the addresses in the virtual memory space corresponding to addresses FFFFF (H) to F4000 (H) in the real memory space are 0 to BFF in bank 1
(H), Bank 2 from C000 (H) to 17FFF (H), and Bank 3 from 18000 (H) to 23FFF (H).
The address conversion from virtual memory to real memory cannot be done easily like at KB. In general:

Ap = INV (A1−Bp × INT (A1 / Bp)) (1) where Ap is the address (physical address) of the real memory space, A1
Is the address (logical address) of the virtual memory space Bp is VBB
INV (X) means that 1 and 0 are reversed when X is expressed in a binary number. See also INT
(X) represents the integer part of X. The conversion means for converting to a logical address as shown in the equation (1) can be generally realized by using a multiplier / divider and an adder / subtractor. Further, when the VBB memory capacity is 2 to the nth power (n is an integer) as in the case of 64 KB, the upper bits are ignored and only the necessary number of bits is used, so that the configuration is simple. As described above, in order to make the VBB area a variable capacity, the address conversion means 32 shown in FIG.
, And its interior is configured to satisfy the function of equation (1).

Next, FIG. 6 shows a memory map when the DRAM block is expanded. This is an example in which only the DRAM block part is used as another printed circuit board (hereinafter referred to as an expansion RAM board) and the memory capacity can be expanded according to the user's wish. In Fig. 6, the left half shows the case where the VBB area is 64KB and there is no expansion RAM board, and the case where one expansion RAM board is added. In the figure, addresses e to h are expanded parts. Here, if the mapping of the VBB area when one expansion RAM board is added is fixed, it is arranged at addresses c to d in the figure. Therefore, the user data area is divided into two, addresses a to b and e to h, so that a continuous user data area cannot be secured and data processing becomes complicated. In order to solve this, the VBB area may be mapped at the end of the memory and the addresses may be changed from g to h as shown in the figure. Generally, even if the memory capacity is expanded, the last address is often all 1 in the number of effective bits, so VDG3 shown in Fig. 1 is used.
Since the means for address generation generated from 5 can be specified in common, the hardware can be easily realized. On the other hand, another method of continuously securing the user data area is to map the VBB area adjacent to the system area. In this case, with the revision of the system,
When the capacity of the system area changes, the VDG35 hardware must be changed, which is extremely inconvenient.
For the above reasons, the VBB area is mapped at the end of the mounted memory in this embodiment. Next, in the right half of Fig. 6, two expansion RAM boards are added and the VBB area is 64KB and 128KB. As shown in the figure, since the VBB area can be made variable, it is possible to easily secure a continuous user data area and to easily manage the user data area. In addition, the VBB area capacity can be optimized according to the amount of data from the user input from the outside, and a system that is resistant to overrun described in the conventional example can be configured. In other words, in the empty area excluding the user data actually stored in the user data area actually stored in the user data area, VBB
It is understood that the VBB memory capacity that can secure the maximum memory capacity as the area is determined and set in the VBB mode switching means of FIG. It is also possible to determine whether or not a sufficient VBB area can be secured, and if possible, fix the memory capacity for one page as the VBB area.
In this case, overrun never occurs. Further, FIG. 6 shows three cases of one expansion RAM board, two expansion RAM boards, and no expansion RAM board, but in order to bring the location of the VBB area to the end, the bank switching means 31 of FIG. 1 must be set appropriately. Just go. The embodiment of the present invention has been described above focusing on the VBB area.

EFFECTS OF THE INVENTION As described above, the present invention is an image output apparatus for bit-expanding and outputting image data to be printed sent from the outside, and processing means for expanding the data to be printed from the outside into a bitmap. A storage means having a storage area for data to be bit-expanded by the processing means and an image storage area for storing image data bit-expanded by the processing means in the same address space; and an image storage area in the storage means Of the print data before the bit expansion and the image after the bit expansion, because the access means for accessing and sequentially outputting the data and the arbitration means for preventing the simultaneous access of the processing means and the access means are arranged. The data storage area and the data storage area can be arranged in the same address space, and the work of increasing the storage capacity is facilitated.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a video data processing unit in one embodiment of the present invention, and FIG. 2 is a block diagram inside the VDG,
FIG. 3 is a memory map diagram showing the virtual memory space and the real memory space, FIG. 4 is the same flowchart, and FIG. 5 is the same VBB.
Figure 6 shows the same memory map when changing the area.
Memory map diagram for expanding DRAM block, No. 7
FIG. 8 is a block diagram of a laser printer, FIG. 8 is a block diagram of a conventional video data processing unit, FIG. 9 is a bitmap data development diagram for explaining overwriting, and FIG. 10 shows a conventional control procedure. It is a flowchart shown. 1 ... Host computer, 2 ... Interface means,
3 ... Video data processing unit, 4 ... LSU unit, 5 ... Engine control means, 6 ... Engine mechanical unit, 42 ... DRAM block unit, 9
… VRAM block part, 12… DRAM arbitration means

 ─────────────────────────────────────────────────── --- Continuation of front page (56) References JP-A-56-22482 (JP, A) JP-A-62-256160 (JP, A) JP-A-2-89284 (JP, A) JP-A-60- 563 (JP, A) JP-A-59-223873 (JP, A) JP-A-53-5944 (JP, A)

Claims (1)

(57) [Claims] 1. An image output apparatus for bit-expanding and outputting image data to be printed, which is sent from the outside, and processing means for expanding the data to be printed from the outside into a bit map, and a bit by the processing means. Storage means having a storage area of data to be expanded and an image storage area for storing image data bit expanded by the processing means in the same address space, and an image storage area in the storage means are accessed and sequentially output. An image output apparatus comprising: an access unit; and an arbitration unit that blocks simultaneous access of the processing unit and the access unit.