JPH06125524A - Video printer - Google Patents

Abstract

PURPOSE:To reduce the load an address control for the data transfer of a controller. CONSTITUTION:A memory 13 is composed of a dual port memory and stores data of an 8-printing line. An L side is connected with the side of a controller 11 (CPU) and a R side is connected with the side of a thermal head. When the controller 11 performs an access to the memory 13, it always performs the access by the same address, the offset value to be written in an offset register 14 is increased every time the printing of one line is terminated, it is added to the logical address outputted from the controller 11 by an adder 15 and it is imparted to the address lines A10 to A12 of the L side. Thus, the controller 11 always performs the access to the memory 13 by the same address, but by adding the offset value to this address, the area of the memory 13 to which the access is actually performed is to be cyclicly changed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video printer, and more particularly to a memory structure and address control for the video printer.

[0002]

2. Description of the Related Art FIG. 5 is a diagram showing a schematic configuration of a conventional video printer, in which image data taken in from a VTR, a TV camera or the like is written in a frame memory 2. The image data written in the frame memory 2 is sequentially transferred to the work memory 3, and R, G, B to Y (yellow),
Color processing such as color conversion to M (magenta) and C (cyan), undercolor removal (UCR) processing, or thermal tailing processing is performed, and the data is written in the line memory 4 or the line memory 5. That is, assuming that the connection is made as shown by the solid line in the figure, the control device 1 performs a predetermined calculation on the image data written in the work memory 3 to generate the print data for one line. Is written in the line memory 4, and the print data written in the line memory 5 at this time is read by a read address from the head control circuit 6 and supplied to a head (not shown), such as a thermal head, for printing. When the printing of the line and the writing of the print data for one line to the line memory 4 are completed, the print data connected to the line memory 4 as shown by the broken line in FIG. The read data is read by the read address and supplied to the head, and the print data of the next print line is written in the line memory 5 by the control device 1. One screen is printed by repeating the above operation.

It is assumed here that one print line is printed as shown by a thick line 9 in FIG. 6 and is sub-scanned in the direction shown by an arrow 10. The number of elements of the head, that is, the number of pixels in the main scanning direction is 1024, and the number of pixels in the sub scanning direction is 1280. The same applies hereinafter. On the contrary,
When printing an NTSC image, the vertical scanning direction of the TV image, that is, the main scanning direction of the video printer is 5
Since 12 pixels are normally sampled to about 640 pixels in the horizontal scanning direction of the TV image, that is, in the sub-scanning direction of the printing of the video printer, the control device 1 is horizontal when writing the image data in the frame memory 2. The processing is performed to double the scanning direction and the vertical scanning direction.

Therefore, assuming that each pixel has 8 bits for each color and 256 gradations, the capacity of the frame memory 2 is 1024 for each color signal of R, G, B respectively.
× 1280 bytes is enough, and line memories 4 and 5 are each 1 kbyte. On the other hand, work memory 3
The required capacity depends on what kind of processing is performed on the image data. For example, simply R, G,
If only the conversion from B to Y, M, and C and the UCR process are performed, the R, G, and B data of one pixel may be fetched into the work memory 3, so the work memory may include the area for writing the calculation result. It is sufficient for 3 to have a capacity of 4 bytes, but in addition to this, when performing thermal tailing processing etc., it is necessary to take in the data of the line to be printed and the lines before and after, so a larger capacity Is required. In addition,
Since the processing after being read from the line memory 4 or 5 is well known, the description thereof will be omitted.

[0005]

However, in the conventional video printer, as shown in FIG. 5, since the work memory and the line memory are separately provided,
It is necessary to transfer the image data from the frame memory to the work memory once, and further to transfer the result obtained by performing the predetermined image processing on the work memory from the work memory to the line memory. The processing for transfer has increased, which not only increases the load but also increases the processing time. Further, since it was necessary to use two line memories, the capacity of the memory increased and the utilization efficiency was poor.

The present invention is to solve the above problems and to reduce the load of address control for data transfer of a control device by minimizing the data transfer and to shorten the processing time. It is an object of the present invention to provide a video printer capable of achieving the above-mentioned advantages and improving the efficiency of memory utilization.

[0007]

In order to achieve the above object, a video printer according to a first aspect of the invention has an input terminal for inputting image data transferred from an external storage device for each print line, and a plurality of input terminals. Memory means capable of accumulating image data for a print line; control means for accessing the memory means when writing image data from the image data input terminal to the memory means and reading image data from the memory means; Address conversion means for adding a predetermined offset value to the address value from the control means, and generating a new address for sequentially accessing the storage area of each print line of the memory means for each print line. Characterize.

The video printer according to claim 2 is
A frame memory capable of accumulating at least one screen of image data, memory means capable of accumulating image data of a plurality of print lines, writing of image data from the frame memory to the memory means, When the image data is read out, the control means for accessing the memory means and a predetermined offset value are added to the address value from the control means, and the storage area of each print line of the memory means is sequentially accessed for each print line. And an address conversion unit that generates a new address that can be generated.

Further, in the video printer according to the first and second aspects, the memory means is composed of a dual port memory.

[0010]

The operation of the video printer according to claim 1 is as follows. The video printer has an input terminal for inputting the image data transferred from the external storage device, and the image data transferred from the external storage device for each print line is transferred to the memory means from this input terminal. Written. This memory means can store image data for a plurality of print lines.

Then, the control means accesses the memory means when writing the image data input to the input terminal to the memory means, but at that time, the address outputted from the control means is directly supplied to the memory means. Instead, the address conversion means adds a predetermined offset value to generate a new address, and the new address is accessed.

Therefore, when writing the image data to the memory means, the offset value added by the address conversion means is cyclically changed so that the control means actually accesses the memory means even when the same address is always accessed. It is possible to cyclically change the print line that is accessed by, and as a result, it is possible to reduce the address control load of the control means.

Further, since data for a plurality of printing lines is written in the memory means, thermal tailing processing and the like can be performed on this memory means. Further, when the memory means is constituted by a dual port memory as described in claim 3, one port can be connected to the control means side and the other port can be connected to the head side, so that one memory device is provided. As a result, it is possible to use both the conventional work memory and the line memory, and it is possible to improve the utilization efficiency of the memory device.

Next, the operation of the video printer according to the second aspect is as follows. Image data to be printed is stored in the frame memory. Data for a plurality of printing lines including a printing line among the image data stored in the frame memory is written in the memory means. The control means accesses the memory means at the time of writing from the frame memory to the memory means, but the address output from the control means at that time is not directly supplied to the memory means, but a predetermined offset value is given by the address conversion means. Is added to generate a new address, which is accessed by this value.

Therefore, when writing from the frame memory to the memory means, the offset value added by the address conversion means is cyclically changed so that the control means actually accesses the memory means even when the same address is always accessed. It is possible to cyclically change the print line that is accessed by, and as a result, it is possible to reduce the address control load of the control means.

Further, since data for a plurality of printing lines is written in the memory means, thermal tailing processing and the like can be performed on this memory means. Further, when the memory means is composed of a dual port memory, one port can be connected to the control means side and the other port can be connected to the head side. Since it can be used also as a memory, the utilization efficiency of the memory device can be improved.

[0017]

Embodiments will be described below with reference to the drawings.
FIG. 1 is a diagram showing a configuration of an embodiment of a video printer according to the present invention. In the figure, 11 is a control device, 12 is a frame memory, 13 is a memory, 14 is an offset register, 1
5 is an adder, 16 is a decoder, 17 is a print control device, 1
Reference numeral 8 indicates a data bus, and 19 indicates an address bus.

The controller 11 writes the image data in the frame memory 12, transfers the image data from the frame memory 12 to the memory 13, and R,
It performs predetermined processing such as color conversion processing from G, B to Y, M, C and thermal tailing processing, and is configured by a microprocessor and its peripheral circuits. The frame memory 12 is the same as the conventional one, and has a capacity capable of storing 1024 × 1280 bytes for each of R, G, and B color signals.

The memory 13 is composed of a dual port memory, the port on the L side is connected to the control device 11 side, and the R
The side port is connected to the head side. Then, as shown in FIG. 2, each print line data, that is, 1
It is divided into eight areas each having a capacity of k bytes.
That is, the memory 13 has a capacity of 8 kbytes. Here, the total address space managed by the control device 11 is 64 kbytes, and C000 _{H to} DFFF _H (H indicates hexadecimal numbers, which is the same hereinafter) are allocated to this memory 13. It is supposed to be. Therefore, as shown in FIG. 2, the area 0 is assigned to the logical addresses C000 _{H to} C3FF _H of the control device 11,
Region 1 is allocated to the logical address C400 _H ~C7FF _H. The other areas are as shown in FIG. In addition, in FIG.
This means that the area 0 is accessed when the 3 bits given to the address lines A _{10 to} A ₁₂ of the memory 13 are (000). The same applies to the other areas. Therefore, the address lines A ₁₀ to
When the 3 bits given to A ₁₂ is (010), area 2 is accessed, and when it is (110), area 6 is accessed. That is, the address lines A _{10 to} A ₁₂ of the memory 13 are used to select the area, and the address lines A _{0 to} A ₉ are used to specify the data of the pixels written in the selected area.

The offset register 14 is intended to store the offset value OF ₀ ~OF ₂ of 3 bits supplied from the control unit 11, the offset value OF ₀ ~OF ₂
Is an adder 15 and an address line A ₁₀ on the R side of the memory 13
Given to A ₁₂ .

The adder 15 adds the 10th to 12th bits of the logical address output from the control device 11 and the offset values OF _{0 to} OF ₂ from the offset register 14 to add the address line on the L side of the memory 13. It is given to A _{10 to} A ₁₂ .
Note that overflow is ignored during addition.

The decoder 16 determines whether or not the control device 11 is accessing the memory 13 based on the values of the 12th bit to the 15th bit of the logical address output by the control device 11, and the control device 11 causes the memory 13 to access. Is accessed, the chip select signal CS is set to a predetermined value, for example, high level. Specifically, as apparent from FIG. 2, the memory 13 has logical addresses C000 _{H to} DF.
Since FF _H is assigned, the decoder 16 determines that the upper 4 bits of the logical address output by the control device 11 are C _{H.
Alternatively} , when it is D _H , the CS signal is set to the high level.
Then, when the CS signal becomes high level, the memory 13 is brought into a writable or readable state.

The print control device 17 is the same as the conventional one, and performs reading of data for one print line from the memory 13, gradation control based on the read data, control of recording paper conveyance, and the like. Further, the print control device 17 gives a line signal line to the control device 11 every time printing of one line is completed.

Next, the operation of the configuration shown in FIG. 1 will be described. First, the outline of the operation of the control device 11 is as follows. The controller 11 recognizes that the data of the line to be printed is always written in the area 0. Therefore, when performing color conversion from R, G, B to Y, M, C, the logical address (A ₁₂ , A ₁₁ , A ₁₀ ) = (00
0) is output to try to access the data written in the area 0. Further, the control device 11 performs the thermal tailing process based on the data written in the area 7, the area 0, and the area 1, and writes the result in the area 0. Therefore, when the thermal tailing process is performed, logical addresses (A ₁₂ , A ₁₁ , A ₁₀ ) = (111), (000), (0
01) is output to access areas 7, 0 and 1, and the result of the processing is the logical address (A ₁₂ , A ₁₁ , A ₁₀ ) = (00
0) is output and an attempt is made to write to area 0. Further, when the printing of one line is completed, the control device 11 tries to write the data of eight lines ahead in the area 7. Therefore, in this case, the logical address (A ₁₂ , A ₁₁ , A ₁₀ ) = (111).

Next, the operation when the print start is instructed will be specifically described. When a print start is instructed from a user interface (not shown in FIG. 1) including a console panel or the like, the control device 11 first causes the offset value (OF ₂ , OF ₁ , O) to the offset register 14.
F ₀ ) = (000) is given, and the logical address (A ₁₂ ,
A ₁₁ , A ₁₀ ) = (000) to (111) are sequentially output to the address bus 19, and the data of the 0th line to the 7th line are sequentially read from the frame memory 12. These logical addresses are added to the offset value by the adder 15. At this time, the offset values (OF ₂ , OF
_{Since 1} , OF ₀ ) = (000), the logical address is given as it is to the address lines A _{10 to} A ₁₂ on the L side.
Therefore, the data of the 0th line to the 7th line read from the frame memory 12 is as shown in FIG. 3A.
It is written in areas 0 to 7 of the memory 13, respectively.

Next, the controller 11 outputs the logical address (A ₁₂ , A ₁₁ , A ₁₀ ) = (000) to access the area 0, reads the data of the 0th line, and performs the color conversion processing. Then, the result is written in the area 0 again. Note that, here, the thermal tailing process is not performed on the data of the 0th line which is the first printing line, but the thermal tailing process is performed using the data of the 1st line which is the next printing line. Of course, the pulling process may be performed.

When the color conversion process is completed, the print control device 17 reads the data of the 0th line from the memory 13, but at this time, the offset values (OF ₂ , OF ₁₎ are applied to the address lines A _{10 to} A ₁₂ on the R side. , OF ₀ ) = (000) is given, the data written in the area 0 is read and supplied to the head.

When the printing of the 0th line is completed, the print controller 17 gives a line signal to the controller 11. As a result, the control device 11 writes the offset value (OF ₂ , OF ₁ , OF ₀ ) = (001) in the offset register 14. Then, in order to perform color conversion processing and thermal tailing processing next, logical addresses (A ₁₂ , A ₁₁ , A ₁₀ ) = (11
1), (000), (001) are output to access the areas 7, 0 and 1, but the offset value (001) is added to these logical addresses by the adder 15, so the L side Address lines A _{10 to} A ₁₂ of (00
0), (001), (010) will be given, and areas 0, 1 and 2 are actually accessed. Then, the control device 11 tries to write the results of these processes to the area 0, and the logical addresses (A ₁₂ , A ₁₁ , A ₁₀ ) = (00
0) is output, but the offset value is similarly added, so that the area 1 is actually accessed and the area 1 is written.

When these processes are completed, the control unit 11 reads out a new print line, in this case the data of the eighth line, from the frame memory 12 and tries to write it in the area 7 with the logical address (A ₁₂ , A). ₁₁ , A ₁₀ ) ＝
Although (111) is output, the offset value (001) is added to this logical address by the adder 15, so (000) is added to the address lines A _{10 to} A ₁₂ on the L side of the memory 13.
Is given, and thus region 0 is actually accessed,
As shown in FIG. 3B, the data of the eighth line is written in the area 0.

When these processes are completed, the print controller 1
7 reads the data of the first line from the memory 13, but at this time, the offset values (OF ₂ , OF ₁ , OF ₀ ) = (001) are given to the address lines A _{10 to} A ₁₂ on the R side. Therefore, the data written in the area 1 is read and supplied to the head, and the first line is printed.

When the printing of the first line is completed as described above, the print controller 17 sends a line signal to the controller 1.
Give to one. As a result, the control device 11 causes the offset register 14 to store the offset values (OF ₂ , OF ₁ , OF ₀ ).
= (010) is written. Then, in order to perform color conversion processing and thermal tailing processing, logical addresses (A ₁₂ , A ₁₁ , A
₁₀ ) = (111), (000), (001) is output to access the areas 7, 0 and 1, but the logical values of these are offset by the offset value (0
10) is added, the address lines A _{10 to} A ₁₂ on the L side are added.
Will be given (001), (010), (011), and areas 1, 2, and 3 are actually accessed. Then, the control device 11 displays the result of these processes in the area 0.
Attempting to write to the logical address (A ₁₂ , A ₁₁ , A ₁₀ )
Although = (000) is output, the area 2 is actually accessed by adding the offset value in the same manner, and the area 2 is actually written.

When these processes are completed, the control device 11 reads out a new print line, in this case, the data of the ninth line from the frame memory 12, and tries to write it in the area 7 by using the logical addresses (A ₁₂ , A ₁₁ , A ₁₀ ) ＝
Although (111) is output, since the offset value (010) is added to this logical address by the adder 15, the address line A _{10 to} A ₁₂ on the L side of the memory 13 is (001).
Is given, and thus region 1 is actually accessed,
As shown in FIG. 3C, the data of the ninth line is written in the area 1.

When these processes are completed, the print controller 1
7 reads the data of the second line from the memory 13, but at this time, the offset values (OF ₂ , OF ₁ , OF ₀ ) = (010) are given to the address lines A _{10 to} A ₁₂ on the R side. Therefore, the data written in the area 2 is read and supplied to the head, and the second line is printed.

The above operation is repeated for all print lines, whereby the printing of the first color is completed. The same applies to the printing of the second and third colors. In addition,
The offset value is returned to (000) after (111).

Although one embodiment of the present invention has been described above, the present invention is not limited to the above embodiment and various modifications can be made. For example, in the above embodiment, the offset register 14 is provided and the control device 11 writes the offset value. However, as shown in FIG. 4, the 3-bit counter 20 is sequentially incremented by the line signal output from the print control device 17. It is also possible to input the output as an offset value to one input terminal of the adder 15 and to supply it to the address lines A _{10 to} A ₁₂ on the R side of the memory 13.

Further, in the above-mentioned embodiment, the data for eight print lines is written in the memory 13, but the present invention is not limited to this, and data for a desired number of print lines can be written. Is.

Further, although the memory 13 is constituted by the dual port memory in the above embodiment, it may be constituted by the single port memory. However, in this case, since the memory is used as a conventional work memory, a line memory is required as in the conventional case, but the effect of the present invention is to reduce the address control load of the control device. It will be apparent to those skilled in the art that this will be achieved. Alternatively, the frame memory may not be built in, and the image data may be transferred from an external storage device such as a computer every time one line is printed.

[0038]

As is apparent from the above description, according to the present invention, the control means is required to always output the same address in the color conversion processing or the thermal tailing processing. Therefore, the processing speed of the video printer can be improved.

Further, since the conventional work memory and the line memory can be used by using the dual port memory, the data transfer from the work memory to the line memory, which has been conventionally required, becomes unnecessary and the data transfer can be prevented. Since the number of times can be reduced, the processing speed of the entire system can be improved.

Further, since the data for a plurality of print lines is written in the memory, it is possible to easily perform the correction process such as the thermal tailing process, which is required to refer to the data of the lines before and after the print line.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a diagram showing a structural example of a memory 13 of FIG.

FIG. 3 is a diagram showing an example of transition of data written in a memory 13.

FIG. 4 is a diagram showing the configuration of another embodiment of the present invention.

FIG. 5 is a diagram showing a configuration example of a conventional video printer.

FIG. 6 is a diagram for explaining a printing direction.

[Explanation of symbols]

11 ... Control device, 12 ... Frame memory, 13 ... Memory, 14 ... Offset register, 15 ... Adder, 16 ...
Decoder, 17 ... Print control device, 18 ... Data bus, 1
9 ... Address bus, 20 ... 3-bit counter.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04N 5/91 H 4227-5C

Claims (3)

[Claims] 1. An input terminal for inputting image data transferred from an external storage device for each print line, a memory means capable of accumulating image data for a plurality of print lines, and the memory from the image data input terminal. When writing the image data to the means and reading the image data from the memory means, the control means that accesses the memory means, and a predetermined offset value are added to the address value from the control means, and the printing is performed for each print line. A video printer, comprising: an address conversion unit for generating a new address capable of sequentially accessing the storage area of each print line of the memory unit. 2. A frame memory capable of accumulating image data for at least one screen, a memory means capable of accumulating image data for a plurality of print lines, and writing image data from the frame memory to the memory means. When the image data is read from the memory means, a control means for accessing the memory means and a predetermined offset value are added to the address value from the control means, and each print line stores each print line of the memory means. A video printer, comprising: an address conversion unit that generates a new address that can access areas in order. 3. The video printer according to claim 1, wherein the memory means is a dual port memory.