JPS59192285A - Image memory circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an image display device, and particularly to an image memory circuit suitable for high-speed data writing into an image memory.

[Background of the invention]

The image information written in the memory is read out and the cathode ray tube (
In image display devices such as CRT (abbreviated as CRT) that display graphics and graphics on a display screen, the amount of information per display pixel tends to increase in order to express more natural images. Image memory has a large capacity, and it takes a lot of time to write data.

FIG. 1 is a diagram showing an example of the bit configuration of such an image memory.
This is an example in which the display screen is divided into 00 lines and 4 bits of information are assigned to each of the three primary colors, KGB, to each of the 11 dots on the display screen.

These 1 pixel unit image information is RG as shown in Figure 2.
Since each B is D/A converted and supplied to the CRf as an analog RGB signal, it is possible to color the display screen in 2'2-4096 ways in units of 11 dots, which is comparable to images using normal analog video signals. It is possible to reproduce natural-looking images.

FIG. 6 is a diagram showing an example of writing image information stored in the image memory shown in FIG. , that pro 5. Write one pixel at a time in the depth direction of the inner block, scanning from the top left to the bottom right as shown in the figure, and when all the blocks are written, all the blocks in the next memory brain in the depth direction are written. I'll go.

In order to write such data, addresses in the image memory are allocated in the depth direction as shown in Figure 4, and the method of allocating all addresses in pixel units is the writing process by a processor (abbreviated as MPU). It's advantageous in terms of speed.

A method of writing image data into an image memory with address allocation as shown in FIG. 5 will be explained using the image memory circuit shown in FIG. In FIG. 5, 1.2 and 3 are data buses, address buses and write control signals connected to the MPU.

4 is an address decoder, 5 and 6 are address selection signals for the image memory 7 and register 9, and 8 is an MP
Writing that inputs and controls the write control signal 3 from U for each chip of the image memory 7! It is an Il# circuit and is constructed like an AND circuit.

As shown in FIG. 4, the image memory 7 has a configuration in which all 12 bits in the forward direction of the display screen are made independent in memory chip units, and the MPU writes information specifying the bits to be written in the register 9 in advance. Then, when data is written to a specific address in the image memory 7, the write control signal 6 from the MPU is logically ANDed bit by bit with the write designation information recorded in the register 9 by the write control circuit 8. taken,
Since the output is supplied in units of 7 hechips to the image memory, data is written only to the bits of the image memory that correspond to the write designation bit recorded in register 9, and no data is written to the bits that are not designated for writing. .

For this reason, even with the writing method shown in Figure 3, in which data is written in blocks in block units, data at a different bit position may be superimposed on an address in the image memory 7 where data has already been written. When writing data, there is no need to calculate the logical sum using software, and if information specifying the pit position to be written is recorded in advance in the register 9, the data to be added can be simply written to the image memory 7 as is. good.

However, in the conventional image memory circuit shown in FIG. 5, the address of the image memory is fixed to the allocation for each data bit in the depth direction. When writing a series of image patterns in the horizontal direction of the display screen in order to transfer them to the image memory, the MPU can only specify addresses in display pixel units. - It is necessary to divide the image into data bits and write image information consisting of coloring information and gradation information in the depth direction for each display pixel, which has the disadvantage of requiring a very long processing time. Was.

[Purpose of the invention]

The object of the present invention is to eliminate the above-mentioned drawbacks of the prior art, and to provide not only high-speed processing for writing continuous image information in the depth direction of one display pixel.

An object of the present invention is to provide an entire image memory circuit capable of processing at high speed the writing of image information of continuous display pixels in the horizontal direction.

[Summary of the invention]

In order to achieve all of the above objects, in the image memory circuit according to the present invention, the image memory is arranged planarly in bit units in the depth direction corresponding to one dot of all display pixels and in arbitrary plurality of bit units in the horizontal direction. Address selection signals are input to the image memory depending on whether continuous image information is written in the horizontal direction or when all continuous image information is written in the horizontal direction. When inputting an address selection signal that selects an address in bit units in the direction, writing image information in the depth direction as data input, and writing continuous image information in the horizontal direction, the data content of the image pattern in the horizontal direction Horizontal view of image memory 1. The data in the register in which image information in the depth direction is recorded in advance is written as data input.

[Embodiments of the invention]

Hereinafter, all embodiments of the present invention will be explained in detail using sounds.

FIG. 6 is a diagram showing an embodiment of an image memory circuit according to the present invention. In FIG. 6, the same parts and signal lines as in the conventional example shown in FIG. 5 are denoted by the same reference numerals, and a description of these reference numerals will be omitted. In Figure 6, 7
・ is the image memory, 1 in the depth direction of the display pixel unit
It is based on a configuration in which 2 bits and 8 beats are arranged two-dimensionally in the horizontal direction. 10 is an address decoder that decodes the lowest 3 bits (A+-A2-As) of the address from the MPU; 11 is an address decoder that decodes the 8 outputs from the address decoder 10 and 8-bit data connected to the data bus 1; It is a switching multiplexer and outputs a memory selection signal 16. 12 is a data register for recording write control information in the depth direction of the display image 1; a 16-digit data bus 1; a multiplexer for switching between the connected 12-bit data and the data recorded in the data register 12; Outputs input signal 17. 14 is a mode setting register that records data that controls all switching of multiplexers 11 and 13; 15 is a chip selector that inputs and controls the image memory address selection signal 5 so that 8 bits in the horizontal direction of the image memory can be selected in units of 1 bit; It is a control circuit and is composed of an AND circuit.

When writing image information in the depth direction for each pixel as shown in FIG. 3 in the image memory circuit shown in FIG.
Step 4: Make settings for writing in the depth direction. The output of this mode setting register 14 serves as a control signal for multiplexers 11 and 13, and outputs multiplexers 11 and 16.
Switch to the side indicated by . Therefore, the memory selection signal 16 is
This becomes the output signal of the address decoder 10, and the chip selection control circuit 15 selects the address of the image memory 7' only from the address decoded chip of the image memory 7' in the depth direction. On the other hand, the data input signal 17 becomes a data bus signal from the MPU and is supplied to the image memory 7'.
Data can be written in the depth direction in units of bits, and the write control circuit 8 and register 9 control the image memory 7.
′ can also be processed at high speed.

In addition, when writing all continuous image information in the horizontal direction of the display screen, the MPU sets the horizontal writing in the mode setting register 14, and switches the multiplexers 11 and 13 to the side shown in (3). Therefore, the memory selection signal 16 input to the image memory 7' becomes a data bus signal from the MPU, and the chip selection control circuit 15 selects the address of the image memory 7' when the data on the data bus is at a level of 1''. Only the bits are selected,
) are not selected. On the other hand, the data input signal 17 becomes a data signal from the data register 12 that specifies the depth direction of the image memory 7', and is supplied as a data input to the image memory 7'. The recorded data is stored in the image memory 7 as is.
' is often written to the selected address.

FIG. 7 shows an example in which image information that is continuous in the horizontal direction of the display screen is written to the image memory, and the data register 12 in FIG. The information and the gradation information of the specified color are recorded as the depth information of the display pixel as shown in the figure, and this figure shows the case where the coloring of the image pattern is "yellow" and the gradation of that color is i7/16. Since the MPU data bus signal for selecting the address of the image memory 7' is an image pattern in the horizontal direction of the display screen to be written to the image memory, the address is selected for the image pattern at a level of 1'', and the data register 12
The depth information recorded in the image memory 7' is written as is in the image memory 7' simultaneously and in parallel. Further, since no address is selected for the level where the image pattern is "+", the depth information in the data register 12 is not written.

In this way, according to this embodiment, it is possible not only to write all the color information and gradation information in the depth direction for each display pixel in units of 1 bit, but also to write an image pattern that is continuous in the horizontal direction of the display screen. When writing, simply record the coloring information and gradation information in the depth direction in the register in advance and write it to the memory for all image patterns, and the image information in the depth direction of consecutive image patterns can also be written in parallel. This eliminates the need to divide a continuous image pattern into units of one display pixel and write all image information such as coloring information in units of addresses in the image memory, as in the conventional case, and high-speed processing can be realized.

Note that in this embodiment, the data register 1 shown in FIG.
2 can be shared with the write control register 9 that specifies and controls write bits in the depth direction when all data is written in the depth direction, thereby achieving the effect of reducing the circuit scale. In addition, in this embodiment, the chip arrangement of the image memory is 8 in the horizontal direction.
Although this is an example of 12 pits in the bit depth direction, the effects of the present invention will remain the same even if the arrangement is other than this.

〔Effect of the invention〕

As described above, according to the present invention, in writing data to an image memory having a plurality of pieces of image information for each display pixel,
Not only when writing image information in the horizontal direction of the display pixels, but also when writing image information in the horizontal direction, the image pattern is divided into bits and the image pattern consisting of color information and kidney tone information is divided in the depth direction. Since it is no longer necessary to write the image information for each address in the image memory, there is an effect that the writing processing speed by software can be greatly improved.

In the description of the present invention, data is written to the image memory in the depth direction and the width direction of the display screen, that is, in the Z direction shown in FIG.
Although only the direction and the X direction have been mentioned, it goes without saying that the present invention is equally effective in combination with the Y direction.

[Brief explanation of drawings]

Fig. 1 is a diagram showing an example of the bit configuration of the image memory, Fig. 2 is a conceptual diagram of the display/read processing of image information for one pixel of the image memory, and Fig. 3 is a diagram showing a method of writing an image tax report to the image memory. 4 is a diagram showing the address assignment of the image memory, and FIG. 5 is a diagram showing the conventional image memory circuit.
FIG. 6 is a block diagram showing an embodiment of the image memory circuit according to the present invention, and FIG. 7 is a diagram showing an example of the embodiment shown in FIG. 6 in which all image information is written in the image memory in the horizontal direction. be. 1...Data bus 2...Address assignment 3.
...Write control signal 4...Address decoder 5...
- Image memory address selection signal 6...Register selection signals 7 and 7'...Image memory 8...Write control circuit 9...Write control data register 10...Address decoders 11 and 13...Multiplexer 12 ...Data register 14...Write mode setting register 15...Image memory selection control circuit 16...Image memory chip selection signal 17...Image memory data input signal No. 17 Second section Third section No. 5 Figure 77 Drawing memory r'tpute'tabes

Claims (1)

[Claims] 1. A memory circuit in which a central processing unit and m series of data bits and m memories connected to an address signal line and a data signal line of the central processing unit,
A memory of a specific series among the m series is selected by the address signal of the central processing unit (memory selection signal generation means for generating a memory selection signal, a memory selection signal from the memory selection signal generation means and the central processing unit). 1. A memory selection switching means for switching the data signal from the processing device and supplying it to the selection signal input of the memory; 1. A data holding means for holding the data of rubits to be written in the k memory; and a take signal from the data holding means. and a data input switching means for switching and supplying the data signal from the central processing unit to the data input of the memory, and a mode for writing data into the memory in units of one series and a mode for writing data in m series simultaneously. When data writing is set for each series, the memory selection signal from the memory selection signal generation means and the take signal from the central processing unit are supplied to the memory selection input and data input of the memory, respectively, When m-series simultaneous writing is set, the memory selection switching means and data input are configured to supply the take signal from the central processing unit and the take signal from the data holding means to the memory selection input and data input of the memory, respectively. An image memory circuit characterized in that it is provided with write mode control means for switching and controlling the switching means. 2. The write mode control means is data holding means for holding write designation data for specifying writing in units of data bits of the memory. and write signal control means for supplying a write signal from the central processing unit to the memory bit by bit based on the take signal from the data holding means.