JPS6076790A - Memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a memory device in which a plurality of two-dimensional memories, such as one-image memories, are provided in the depth direction.

[Background Art and Important Points] Various drawing methods are used in response to commands in computers with graph ink functions, terminal devices in videotex systems, and other devices with graphic functions. If an attempt is made to support these drawing methods using a memory device that only has a specific write function, such as a conventional memory device, one write operation must be performed multiple times, which complicates the processing.

As shown in FIG. 1, it is assumed that the following two types of data are written into an image memory having a shape having a horizontal direction X, a vertical direction Y, and a depth direction Z.

■Write zy data for one pixel at certain coordinates (X, y) in the depth direction.

(2) Write 0 to 166 pixels 1vISB (most significant bit) in the horizontal direction χG from a certain coordinate (χo, yo).

If the memory device has only the writing method (■), the method (■) must be repeated 16 times in order to write the amount written in (■).In other words, the data for one pixel in the depth direction Z must be Read and set only the MSB to 0
Process 2 to rewrite to the original address in depth direction 2
You need to repeat it 16 times.

``Object of the Invention'' The present invention is an implementation plan of a memory device that can support writing methods in two directions, the depth direction and one of the horizontal or vertical directions, which is particularly necessary among various drawing methods. This invention is capable of supporting two writing methods, so compared to conventional memory devices that only have m- writing methods, the number of memory accesses can be reduced, and the processing speed can be reduced. It is possible to simplify and speed up the process.

"Summary of the Invention" The present invention relates to a memory device having a two-dimensional memory arranged as a plurality of chips in the depth direction.

"The depth direction and one of the horizontal or vertical directions of the two-dimensional memory are the first and second directions, respectively, and the first direction =I- is common to the plurality of chips. a data line is provided in the plurality of chips G in the second direction;
For this, a common write enable pulse supply line is provided, and the write data in the first direction is supplied to the data line G, and the write enable pulse is supplied by the write data in the second direction. No line to control.

This is a memory device in which a plurality of bits are written once in each of the first and second directions.

"Example" An embodiment of the invention will be described with reference to the drawings.

This embodiment is adapted to support writing in both the depth direction and the horizontal direction. In FIG. 2, 1 indicates an arithmetic processing section, and 2 indicates a memory. The arithmetic processing unit 1 includes a microprocessor 2 and decodes drawing commands.

It is a device that executes. The drawing command is data that instructs which pixel, in which direction, and in what manner, data is to be written. The memory 2 is an image memory having a configuration 2 which will be described later.

A data bus 3 from the arithmetic processing section 1 is led to a chip select controller 41, a data select controller 5, and a multiplexer 6. Also.

An address bus 7 from the arithmetic processing section 1 is led to a memory 2 and a decoder 8. The output of this decoder 8 is supplied to a multiplexer 6, and the output of the multiplexer 6 is supplied to a mask circuit 9. The arithmetic processing unit 1 sends control signals s1. to the chip select controller 4. Data selection function) Control signal S for o-55
2. The multiplexer 6 & the control signal s3° generates a write pulse wP which is supplied to the mask circuit 9.

The chip select controller 4 is for selecting a chip in the memory 2 to which data is to be written.

Generates chip select signals C8, to C8n. The data selection controller 5 controls what is selected as the 7-digits to Dn to be written into the memory 2. The decoder 8 decodes, for example, the lower two bits of the address data and generates a signal for selecting the memory bit 12 to be written. The multiplexer 6 selects the output of the decoder 8 Jj~1 and supplies it to the mask circuit 6 when writing in the depth direction, and selects the data on the data bus 3 and supplies it to the mask circuit 9 when writing in the horizontal direction. supply.

The hunt roll signal S switches the multiplexer 6 in response to this difference in writing direction.

The arithmetic processing unit 1 sends chip select signals C81 to C8n to the data bus 30, firstly sends out data D1 to Dn of 0 or 1, and then sends mask data. Control signals 81, S2 and S3
causes the chip select controller 4, the data select controller 5, and the multiplexer 6 to output a predetermined set of sequentially generated data. Mask circuit 9
When the light pulse WP is out of supply, the multiplexer 6
A predetermined write enable signal WEANWED is formed based on the mask data output from the mask data.

FIG. 3 shows the configuration of a memory chip in an embodiment G of the present invention. A, -An, B, ~B n+C1~C1
1+D1 to Dn each represent a memory chip, and the size of each memory chip is equal to 1. - As an example 1 each memory chip has (χ = 64 bits) (Y = 256 bits II' (Z
= 1 bit), and four memory chips A□, Bi, Ci+Di are arranged in the horizontal direction χ2:l
L, n memory chips A1 to AH+B1 in the depth direction
~Bn, C1~Cn+D, ~Dn are arranged.

What is the correspondence between these memory chips and drawing areas?

The one shown in Figure 4 is similar to the one shown in Figure 4. The drawing area is 7 (256×256) pixels, for example, and n memory areas exist in the depth direction of each pixel. Each of these 11 memory areas is a set of 4 memory chips A1 to D, ,
A2-D2. ---Formed by An-Dn.

Each memory chip is as described above (64X256.=2
) when it has an address.

Four memory chips of the same group having the same address are arranged horizontally, forming a total memory area of (256×256). In FIG. 4, n bits in the depth direction, for example 14 bits, are data for one pixel.

Memory chip A1+13□, Ci, I) 1 at address J of i
Shows bits.

As shown in FIG. 5, among the plurality of memory chips, four memory chip groups A1 to A2 to D2 are arranged in the horizontal direction.
．． ...1～. A common data bus and chip select signals are provided for each set of data D, , D2...Dn and chip select signals cs, , as, , for each set.・・・・・・
...C3r1 are supplied respectively. Write enable signals wEA, WEB, WEC, and WED are applied to memory chips A1 to Ao, +31 to rtn, and c arranged in G rows in the depth direction, respectively.
.

It is applied to a write enable signal supply path provided in common for each set of ~C, ,D, and ~Dn.

Although not shown, the address bus is provided in common to all 4n memory chips.

'' Two series of operations in the case of writing data in the depth direction Z according to an embodiment of the present invention will be explained. With this writing method,
A multiplexer 6 selects the output of the decoder 8 and supplies it to a mask circuit 9.

A chip select signal sent from the arithmetic processing unit 1 to the data bus 3 is supplied to the chip select controller 4,
Chip select signals C81 to C8n are generated to select a chip to be written to among n sets of four memory chips arranged in the horizontal direction χ. Next, the arithmetic processing unit 1
The write data output from the controller is supplied to the data select controller 5. This write data is controlled by a control signal S2 so that it is output to the memory 2 as it is.

For example, a 16-bit address is output from the arithmetic processing unit 1 to the address bus 7, of which the 2nd 14 bits are supplied to all chips G of the memory 2, and the 1st and 2nd bits are supplied to all chips G of the memory 2.
The bits are provided to a decoder 8. F' of this address
The first two bits indicate the four memory chips A included in one set.
Specify the memory chip to be written to among steps D1 to D1.

Output L+ of decoder 8 (IIgu+++, z 7' l
+hCru△1AmasuHEUQc,-(The write pulse WP is applied so that the write enable signal V/E A~WED is output only to the 1st memory chip that is supplied with 1H and selected 9th.
is masked. Generation of this selected write enable signal completes re-entry in the depth direction.

Next, the operation when writing data in the horizontal direction χ will be explained. For example, a case will be explained in which data O is written only to one of four memory chips A1+B1+C1, I. In the case of writing in the horizontal direction X, the multiplexer 6 is controlled by the control signal S3 so as to select the data sent via the data bus 3.

First, memory chips A1 to D are selected by chip select signals C8 and C8n.

Data is output to the chip select controller 4. A control signal S2 is outputted so that O is outputted from the data select controller 5 to the memory 2. In other words, all data of [D, ~D] are set to 0.

Data for masking is generated from the arithmetic processing unit 1 on the data bus 30, and is supplied to the masking circuit 9 via the multiplexer 6.

A write enable signal WEA-7WED is generated for a predetermined memory chip among A1 to D to perform a write operation.
:、Tru.

"Application example" Instead of the data D1 to Dn supply lines in FIG.
Instead of ED supply line ζ, data I) A-DD supply line'? i: It is also possible to provide a configuration. At this time, data DA to DD become data in the horizontal direction, and the first data 2 masked with data in the depth direction are used as write enable signals WE1 to WEn.

Further, the present invention can be similarly applied to the case of configuring a memory device that can handle writing in either the depth direction Z or the vertical direction Y.

Furthermore, in this invention, in the horizontal or vertical direction, 4
Any number of memory chips other than the number may be provided.

[Effects of the Invention] According to the present invention, it is possible to realize a memory device in which the writing direction is in two directions: the depth direction and the horizontal or vertical (force) direction. therefore.

This invention can be applied when it is required to draw images on an image memory using different methods.

Compared to memory devices that only have a single write direction,
Data processing can be made simpler and faster.

[Brief explanation of the drawing]

Fig. 1 is a route diagram showing the configuration of a memory device to which the present invention can be applied, Fig. 2 is a block diagram of an embodiment of the invention, and Figs. 3 and 4 are an embodiment of the invention. G,X
A TKiJ diagram shows the structure of the memory used, and FIG. 5 is a block diagram showing the interconnection relationship between memory chips in an embodiment of the present invention. 1... Arithmetic processing unit, 2... Memory, 3...
...Data bus, 7...Address bus, AH+ B+
...-Cn, Dn... Memory chip.

Claims (1)

[Scope of Claim] A memory device having a two-dimensional memory arranged as a plurality of chips in the depth direction. The depth direction and one direction of the horizontal or vertical direction of the two-dimensional memory are first and second directions, respectively, and a common data line is provided for the plurality of chips in the first direction. , providing a common write enable pulse supply line for the plurality of chips G in the second direction;
The write data in the first direction is supplied to the data line G, and the write enable pulse supply line is controlled by the write data G in the second direction. A memory device designed to allow multiple bits to be written at once.