JPH0528754A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To realize the memory with a pixel align function which a power consumption is reduced, and the word data at an arbitrary location in a memory cell array can be accessed by a location designation with bit units. CONSTITUTION:Word lines are driven by a row decoder(RD) 2 of blocks 6-1-6-4, and block selecting signals BS1-BS4 are outputted by a block selecting circuit (BS) 1. OR gates 8-11 receive the block selecting signals BS1-BS4, and generates signals BA1-BA4 for activating the selected one block, and an upper one block. The selected block and the following block are simulatneously activated by the block selecting circuit 1, and the OR gates 8-11. A column decoder 3 generates a signal indicating the position of the word data of word units, a column selecting gate control circuit 7 generates the signal for selecting the word data, and a column selecting gate 4 allows the access of the word data to be attained between a memory cell array 6 and a data bus 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a block activation circuit which is effective when used as a video memory used as a frame memory for an image in information equipment such as a personal computer and a workstation. It is about.

[0002]

2. Description of the Related Art Generally, a video memory is used as a frame buffer for storing display data in a graphic display device for displaying characters and graphics. With the progress of semiconductor technology, the memory capacity of a video memory integrated on one chip has been increasing. Increasing the memory capacity with one chip is effective in reducing the mounting area on the board,
Similarly, the power consumption of the chip is increasing, which causes a problem that a desired package cannot be used.

As a means for reducing power consumption in a large capacity video memory, a method of activating only a block to be accessed in a memory cell array divided into a plurality of blocks is adopted. FIG. 2 is a configuration diagram of a memory divided into a plurality of blocks as described above. In the figure, an example in which a memory cell array is divided into four is shown, which is accessed by data of a plurality of bit widths (hereinafter referred to as word data). The case where this word data is 4 bits is shown.
Reference numeral 6 denotes a memory cell array, which is divided into 4 blocks, and each block is 6-1, 6-2, 6-3, 6-4. 1 is a block selection circuit (BS) which receives an address indicating a block to be accessed and generates a block selection signal, 2 is a row decoder RD, 3 is a column decoder which decodes a column address, and 4 is driven by an output of the column decoder 3. The column selection gate 5 is an internal data bus.

In the above structure, when a row address is input, an arbitrary word line is driven by the row decoder (RD) 2 in each of the blocks 6-1, 6-2, 6-3 and 6-4, and at the same time, Only one specific block is activated by the outputs BS1 to BS4 of the block selection circuit (BS) 1. Next, when the column address is input, a signal indicating the position of arbitrary word data is generated by the column decoder 3, and the word data accessed by the column selection gate 4 is selected in response to this signal to select the memory cell array 6 The word data is accessed between the data bus 5 and the data bus 5.

FIG. 3 shows a display screen in the graphic display device when the memory having the structure shown in FIG. 2 is used as a frame buffer of the graphic display device. In FIG. 3, reference numeral 8 denotes a display screen, which corresponds to the memory bitmap shown in FIG. 2, and areas 1 to 4 correspond to blocks 6-1 to 6-4 of the memory cell array. There is. When the word data at the position 9-1 on the display screen 8 is accessed, the block selection circuit 1
Output BS2 of is activated and block 6-2 in the memory is activated. When accessing the word data at the position 9-2, the block 6-3 is similarly activated. As described above, in the conventional memory, the memory is divided into a plurality of blocks and only the block to be accessed is activated to reduce the power consumption.

[0006]

When the number of elements that can be integrated on one chip increases, in the video memory, not only the storage capacity is increased, but also a new function is added from the viewpoint of improving the performance of the image display device. Is desired. The new functions are a logical operation function for write data and a pixel align function that allows word data at an arbitrary position in the memory cell array to be accessed by specifying a position in bit units. Display data is processed and displayed in pixel (bit) units, and the pixel align function is effective for improving the performance of the image display device. In order to realize this pixel-alignment function, in the conventional memory in which only the block to be accessed is activated for power consumption reduction, when the word data to be accessed exists across two blocks of the divided memory cell array. Moreover, the word data is divided and only some of the bits can be accessed. Therefore,
In order to access one word of data, two blocks are accessed for two cycles and a complicated process of synthesizing outside the memory is required.

As another method for realizing the pixel align function, all blocks are activated at the same time without using the conventional configuration for reducing power consumption, which activates only designated blocks. You have to take a method. In this way, the pixel alignment function and low power consumption are in conflict.

The present invention has been made in view of the above problems, and is provided with a pixel align function capable of reducing power consumption and allowing word data at an arbitrary position in a memory cell array to be accessed by specifying a position in bit units. And a semiconductor memory device.

[0009]

In order to achieve the above object, the present invention simultaneously provides a memory cell array divided into a plurality of blocks, a block selected by a designated address of the plurality of blocks, and a block continuous with the block. A means for activating, a column selection gate control circuit for selecting a word by bit-wise position designation, and a column selection gate for selecting word data from the memory cell array by the output of the column selection gate control circuit It has a different configuration.

[0010]

According to the present invention, since the block corresponding to the internal address of the divided block and the block succeeding to the divided block are activated at the same time according to the above structure, it is possible to access the word data extending between the divided blocks. Becomes Further, since the block unrelated to the word data to be accessed can be deactivated, the current consumption can be reduced.

[0011]

1 is a block diagram of a semiconductor memory device according to an embodiment of the present invention. The configuration of FIG. 1 will be described below with reference to FIG. In FIG. 1, 6 is a memory cell array, which is divided into 4 blocks, and each block is divided by 6-1 and 6
-2,6-3,6-4. 1 is a block selection circuit (BS) which receives an address indicating a block to be accessed and generates a block selection signal, 8 to 11 are OR gates, 2
Is a row decoder (RD), 3 is a column decoder for decoding a column address, 7 is a column selection gate control circuit for controlling pixel alignment, 4 is a column selection gate driven by the output of the column decoder 3, and 5 is an internal data bus. Is.

In the above structure, when a row address is input, an arbitrary word line is driven by the row decoder (RD) 2 in each of the blocks 6-1, 6-2, 6-3, 6-4, and at the same time, The output of the block selection circuit (BS) 1 outputs signals BS1 to BS4 for selecting a specific one block corresponding to an address. OR gate 8 ~
11 receives block selection signals BS1 to BS4, and receives BS1
Signals BA1 to BA4 for activating one block selected by BS4 and one higher block are generated. Each block 6-1, 6-2, 6-3, 6-4 has an activation signal BA.
1-BA4 activated. For example, block 6-
When an address for selecting 2 is input, BS2 is selected, and this signal activates BA2 and BA3, activating block 6-2 and block 6-3.
In this way, the block selection circuit 1 and the OR gates 8-11
Thus, a means for simultaneously activating a block selected by a designated address and a block succeeding the block is realized.

Next, a column address is input. This column address is used for word data access at an arbitrary bit position, and the head bit position of the word data is given as an address. The column decoder 3 operates similarly to the conventional example shown in FIG.
A signal indicating the position of data in word units is generated by a column address indicating the position of data in word units.
In response to the signal indicating the position of the word data and the address indicating the bit position within the word, the column selection gate control circuit 7 generates a signal for selecting the word data at the arbitrary bit position. The column selection gate 4 selects an arbitrary word data in the memory cell array 6 in response to a signal from the column selection gate control circuit 7 and outputs the selected word data to the data bus 5 to set an arbitrary bit position between the memory cell array 6 and the data bus 5. The word data is accessed at.

FIG. 3 shows a display screen in the graphic display device when the memory having the configuration shown in FIG. 1 is used as a frame buffer of the graphic display device. In FIG. 3, reference numeral 8 denotes a display screen, which corresponds to the memory bitmap shown in FIG. 2, and areas 1 to 4 correspond to blocks 6-1 to 6-4 of the memory cell array. There is.

In word data access at an arbitrary bit position on the display screen shown in FIG. 3, the column address (the position of the first bit of the word data) corresponding to the horizontal position of the screen is 9-1 or 9-3. In the area 2 as described above, the operation of the memory in FIG. 1 is as follows. First, when a row address is input, each block 6-1 and 6
-2, 6-3, 6-4 row decoder (RD) 2
By this, an arbitrary word line is driven, and at the same time, the output of the block selection circuit (BS) 1 activates a signal BS2 for selecting a specific one block corresponding to an address. In response to this signal, the OR gates 8 to 11 activate the block activation signals BA2 and BA3 to activate the blocks 6-2 and 6-3.

Next, when the column address is input, the column decoder 3 outputs the position in word units to the column selection gate control circuit 7. The column selection gate control circuit 7 specifies the word data at an arbitrary bit position by the signal from the column decoder 3 and the address indicating the bit position, and drives the column selection gate 4. The column selection gate 4 outputs word data at an arbitrary bit position to the data bus 5. In the case of accessing the word data 9-1 in the display screen shown in FIG. 3, the internal data bus 5 is connected to the word data in the block 6-2 by the column selection gate 4 to access the word data 9-2. In the case of access, the internal data bus 5 is connected to the word data in the blocks 6-2 and 6-3.

As described above, according to the present embodiment, by designating the position of the leading bit of the designated word data, the blocks that are continuous with the designated block are activated at the same time, so that the word data can be accessed at any bit position. The pixel align function can be realized.

In this embodiment, the case where the memory cell array is divided into four blocks has been described, but the present invention is not limited to the number of block divisions.

[0019]

As is apparent from the description of the embodiments, according to the present invention, blocks irrelevant to word data to be accessed are inactivated, and in a memory with reduced current consumption, position specification can be performed in bit units. The pixel align function that accesses word data can be realized, and the number of blocks that are activated at one time can be reduced compared to the method that activates all blocks at the same time, so the peak current can be suppressed and the noise due to the current can be reduced. Can be reduced, which facilitates the design. Further, by using the semiconductor memory device of the present invention, it is possible to realize a high performance graphic display device.

[Brief description of drawings]

FIG. 1 is a memory configuration diagram of a low current consumption and pixel alignable memory according to an embodiment of the present invention.

FIG. 2 is a conventional memory configuration diagram

FIG. 3 is a diagram illustrating a word line state of a pixel align function on a screen and correspondence with a memory.

[Explanation of symbols]

1 block selection circuit (BS) 2 Row decoder (RD) 3 column decoder 4 column selection gate 5 Internal data bus 6 memory cell array 7 Column select gate control circuit

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Akihiro Matsumoto             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd.

Claims (2)

[Claims] 1. A semiconductor memory device for accessing data in word units of a plurality of bit widths, comprising a memory cell array divided into a plurality of blocks, a block selected by a designated address of the plurality of blocks, and a block continuous with the block. Means for simultaneously activating blocks, a column selection gate control circuit for selecting a word by bit-wise position designation, and a column selection for selecting word data from the memory cell array by the output of the column selection gate control circuit A semiconductor memory device having a gate. 2. A block selecting circuit for activating a block selected by a specified address and a block succeeding the selected block out of a plurality of blocks according to claim 1 by a specified address, and the block selecting circuit. A semiconductor memory device comprising a gate circuit for adding signals corresponding to consecutive blocks among the outputs of the above.