JPH0737378A - Memory element - Google Patents

Abstract

PURPOSE:To rapidly paint out an arbitrary region within a memory, especially a region which is long in column direction. CONSTITUTION:With a storage means 4, memory cells are laid out in a matrix. The column address of the storage means is decoded by a column address decode 1. The row address of the storage means is decoded by a row address decode 2. Input data are stored temporarily in a color register 5 and input data are written into the memory cell which is selected by the column address decode and the row address decode (first data input). The data of color register are written simultaneously in the memory cell for a plurality of column addresses regardless of the lower number bit of the column address (second data input). The first data input and the second data input are switched over at need.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a memory device used in an apparatus such as an image processing apparatus that needs to write the same data into a plurality of memory cells at high speed.

[0002]

2. Description of the Related Art Generally, as this type of memory device, a semiconductor memory device disclosed in Japanese Patent Laid-Open No. 3-157894 is known.

Generally, when writing data in a memory device, a row address and a column address are input and a normal write cycle for writing data only in a designated memory cell and after writing data in a register inside the memory device, There is a block write cycle for writing the data of the register to the memory cells corresponding to a plurality of column addresses regardless of the lower order bits of the column address by inputting the row address and the column address.

[0004]

In the memory device described above, when writing the same data to a plurality of addresses continuous in the row direction, the block write function exists as described above, so that high speed processing is possible, but in the column direction. When writing the same data to a plurality of consecutive addresses, only one address can be written by one access, resulting in a problem that the processing speed becomes slow.

An object of the present invention is to provide a memory device capable of high-speed processing even when writing the same data to a plurality of addresses continuous in the column direction.

[0006]

According to the present invention, storage means in which memory cells are arranged in a matrix, row address decoding means for decoding a row address of the storage means, and column address of the storage means are decoded. A column address decoding means, a data temporary storage means for temporarily holding input data, a first address data writing means for writing the input data into a memory cell of the storage means selected by the row address decoding means and the column address decoding means. Data input means, second data input means for simultaneously writing the data of the data temporary storage means to a plurality of row addresses regardless of the low-order bits of the row address;
There is obtained a memory device characterized by having the data input means and the switching means for switching the second data input means.

Further, in the memory device according to the present invention, third data input means for simultaneously writing the data of the data temporary storage means to a plurality of column addresses regardless of the lower order bits of the column address, and the second data input means. The data input means and the third data input means are used together to write data into the memory cells corresponding to a plurality of row addresses and column addresses regardless of the lower-order bits of the row address and the lower-order bits of the column address. It is characterized in that it has a fourth data input means, and a switching means for switching to the third data input means and the fourth data input means.

In addition, the memory device according to the present invention is characterized in that it has a data mask means for masking writing of arbitrary bits in the depth direction of data.

The memory device according to the present invention further includes a row direction mask means for masking writing of any row address in the row direction of the memory array, and a mask of writing any address in the column direction of the memory array. Column direction masking means.

[0010]

EXAMPLES The present invention will be described below with reference to examples.

With reference to FIG. 1, this embodiment has a function of writing the same data to four consecutive row addresses regardless of the lower 2 bits of the row address.
A memory element having a bit, a column address of 9 bits, and an input / output data width of 4 bits is taken as an example. Top row address decoder 1a decodes the address A2-A8, 2 ⁹
Select four rows in the memory cell array 4 having rows. The lower row address decoder 1b decodes the addresses A0 to A1 and writes one of the four rows selected by the upper row address decoder 1a into a normal write mode, and ignores the addresses A0 to A1. There is a block write mode in which all four rows selected by the upper row address decoder 1a are writable, and a control signal BWE for mode switching is input. The column address decoder 2 decodes the addresses A0 to A8 to generate 2 ⁹
Make one of the columns writable. Sense amplifier I
The / O controller 3 supplies data to the memory cell array 4 which is writable in both rows and columns. The color register 5 stores data used in the block write operation in advance, and outputs the data to the sense amplifier / I / O controller.

FIG. 2 is a timing chart in the block write mode of the memory device shown in FIG. Or later,
The operation of the memory device shown in FIG. 1 will be described with reference to the timing chart of FIG.

At the timing of t2 in FIG. 2, that is, at the fall of the row address strobe signal RAS, the row address is taken into the row decoder 1. At this time, the output enable signal OE is HI and the mode switching signal BWE is HI. In case of block write mode, address A
0 to A1 are ignored, and all the row addresses RN0 to RN3 selected by the row address decoder 1a can be written. Next, at the timing of t4, that is, at the falling edge of the column address strobe signal CAS, the column address is fetched and decoded by the column decoder 2 so that one column address CM can be written. At this time, the data previously set in the color register 5 is the sense amplifier I
The memory cells SN0 to SN3 in which both the row address and the column address can be written through the / O controller 3.
Will be written at the same time.

Next, a second embodiment of the present invention will be described. Referring to FIG. 3, in this embodiment, the sense amplifier / I / O controller 3 to the memory cell array 4 of FIG.
Data input line connected to the data direction mask control circuit 6
Write-controlled by. The memory cells SP0 to SP3 are respectively connected to the memory planes P0 to P.
3 is a memory cell selected by the row address decoder 1 and the column address decoder 2 during block write.

Hereinafter, as an example of the mask function, the case of masking the memory plane P1 will be described. FIG. 4 is a timing chart when the writing is masked in the depth direction of the data. The operation mode of the memory element is the block write mode, and the operation of selecting the memory cells of 4 rows × 1 column is the same as in FIG. The mask function in the data direction becomes valid when the write enable signal WE is LOW at the timing of t2, and the data signal D at that time
The values 0 to D3 are taken into the data direction mask control circuit 6 as mask data. When controlling so that the mask data is HI for no masking and LOW for masking, if it is desired to mask the memory plane P1, D0 to D3 = 1
Enter 011. When the data of the color register 5 is written in the selected memory cell, the writing of SP1 is prohibited by the data direction mask control circuit 6, and SP0
~ Only SP2 and SP3 are written. The mask data can be arbitrarily set by inputting from the data signals D0 to D3 at the timing of t2.

Next, a third embodiment of the present invention will be described. Referring to FIG. 5, in this embodiment, the mask control circuit 7 performs write control on the row address line connected from the lower row decoder 1b shown in FIG. 1 to the memory cell array 4. The memory cells SN0 to SN3 are memory cells selected by the row address decoder 1 and the column address decoder 2 at the time of block write.

Hereinafter, a case where the memory cell SN2 is masked will be described as an example of the masking function. FIG. 6 is a timing chart for masking writing in the row direction according to the present invention. The operation mode of the memory element is the block write mode, and the operation of selecting the memory cells of 4 rows × 1 column is the same as that described in the above (first embodiment). The masking function in the row direction is valid when the mode switching signal BWE is HI and the write enable signal WE is HI at the timing of t2, and the values of the data signals D0 to D3 at that time are taken into the row direction mask control circuit 7 as mask data. Be done. When controlling so that the mask data is HI for no masking and LOW for masking, when it is desired to mask the memory cell SN2, D0 to D3 = 11.
Enter 01. The row direction mask control circuit 7 inhibits writing of RN2 among the row addresses RN0 to RN3 selected by the row decoder 1. The data of the curry register 5 can be written into the memory cell S in which both row and column can be written
Only N0 to SN1 and SN3 are written. The row-direction mask data can be arbitrarily set by inputting from the data signals D0 to D3 at the timing of t2.

Next, a fourth embodiment of the present invention will be described. FIG. 7 is a block diagram showing the configuration of an embodiment of a memory element in the fourth embodiment of the present invention. This figure is
The column decoder in FIG. 1 has the same configuration as the row decoder, and has a block write function in the row direction and a block write function in the column direction. The upper column address decoder 2a is
The addresses A2 to A8 are decoded, and 4 columns in the memory cell array 4 having 2 ⁹ columns are selected. The lower column address decoder 2b decodes the addresses A0 to A1 and writes one of the four columns selected by the upper column address decoder 2a into a normal write mode, and ignores the addresses A0 to A1. Upper column address decoder 1a
There is a block write mode in which all four columns selected by are writable, and a control signal BWE for mode switching is input.

FIG. 8 is a timing chart when block writing is performed for both rows and columns of the memory element according to the fourth embodiment of the present invention. Hereinafter, the operation of the memory device shown in FIG. 7 will be described with reference to the timing chart of FIG. The row address is taken into the row decoder 1 at the timing of t2, that is, at the fall of the row address strobe signal RAS. At this time, if the output enable signal OE is HI and the mode switching signal BWE is HI, the row direction block write is performed. Mode is entered, addresses A0-A1 are ignored,
All the row addresses RN0 to RN3 selected by the row address decoder 1a can be written. Next, t4
The row address is taken into the column decoder 2 at the timing of, that is, at the falling edge of the column address strobe signal CAS. At this time, the output enable signal OE is HI,
When the mode switching signal BWE is HI, the block write mode is similarly set in the column direction, the addresses A0 to A1 are ignored, and all the column addresses CM0 to CM3 selected by the column address decoder 2a can be written.
Then, the data previously set in the color register 5 is simultaneously written through the sense amplifier / I / O controller 3 to the memory cells SN0 to SN15 in which both the row address and the column address are writable.

Next, a fifth embodiment of the present invention will be described. FIG. 9 is a block diagram showing the configuration of an embodiment of a memory element in the fifth embodiment of the present invention. This figure is
The data input line connected from the sense amplifier / I / O controller 3 of FIG. 7 to the memory cell array 4 is write-controlled by the data direction mask control circuit 6. Further, the memory cells SP0 to SP3 are memory cells selected by the row address decoder 1 and the column address decoder 2 in the block write in the memory planes P0 to P3, respectively.

Hereinafter, as an example of the mask function, the case of masking the memory plane P1 will be described. Figure 10
FIG. 13 is a timing chart for masking writing in the depth direction of data according to the fifth embodiment of the present invention. The operation in which the operation mode of the memory element is the block write mode for both rows and columns and the memory in the region of 4 rows × 4 columns is selected is the same as described above (fourth embodiment).
The masking function in the data direction is valid when the write enable signal WE is LOW at the timing of t2, and the values of the data signals D0 to D3 at that time are taken into the data direction mask control circuit 6 as mask data. When controlling so that the mask data is HI for no masking and LOW for masking, when it is desired to mask the memory plane P1, D0 is used.
Input ~ D3 = 1011. When the data in the color register 5 is input to the memory cell array 4, SP1 is masked by the data direction mask control circuit 6, and only SP0, SP2, and SP3 are written. The mask data can be arbitrarily set by inputting from the data signals D0 to D3 at the timing of t2.

Next, a sixth embodiment of the present invention will be described. FIG. 11 is a block diagram showing the structure of a memory device according to the sixth embodiment of the present invention. In this figure, the mask control circuit 7 performs write control on the row address line connected to the memory cell array 4 from the lower row decoder 1b in FIG.
The mask control circuit 8 writes and controls the column address line connected from the lower column decoder 2b to the sense amplifier / I / O controller 3. Further, the row addresses writable in the row direction block write operation are RN0 to RN3, and the column addresses writable in the column direction block write operation are CM0 to CM3.

Hereinafter, as an example of the mask function, a case of masking the row address RN2 and the column address CM3 will be described. FIG. 12 is a timing chart when the writing is masked in the row direction in the sixth embodiment of the present invention. The operation in which the access mode of the memory element is the block write mode for both rows and columns and the memory cells in the region of 4 rows × 4 columns are selected is the same as that described in claim 4.
In the mask function in the row direction, the mode switching signal BWE is HI and the write enable signal WE is H at the timing of t2.
When it is I, it becomes valid, and the values of the data signals D0 to D3 at that time are taken into the row direction mask control circuit 7 as mask data. The masking function in the row direction is valid when the mode switching signal BWE is HI and the write enable signal WE is HI at the timing of t4, and the data signal D at that time is obtained.
The values 0 to D3 are taken into the column direction mask control circuit 8 as mask data. When controlling so that the mask data is HI without mask and LOW to mask, when D0 to D3 = 1110 is input at the timing of t2 and D0 to D3 = 1110 is input at the timing of t4, the row address RN2 and the column are input. Writing to the address CM3 is prohibited. The mask data in the row direction is at the timing of t2, and the mask data in the column direction is at the timing of t4.
By inputting from ~ D3, both rows and columns can be masked arbitrarily.

[0024]

As described above, in the memory device according to the present invention, the same data can be simultaneously written in a plurality of memory cells by the block write in the row and column directions, and the mask in the row and column directions can be arbitrarily performed. Therefore, there is an effect that operations such as filling the area can be performed at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a memory device according to the present invention.

FIG. 2 is a timing chart of block write in the memory device shown in FIG.

FIG. 3 is a block diagram showing a second embodiment of a memory device according to the present invention.

FIG. 4 is a timing chart of block write when masking in the data depth direction is performed in the memory device shown in FIG.

FIG. 5 is a block diagram showing a third embodiment of a memory device according to the present invention.

FIG. 6 is a timing chart of block write when masking in the row direction is performed in the memory device shown in FIG.

FIG. 7 is a block diagram showing a fourth embodiment of a memory device according to the present invention.

8 is a timing chart of block write in row and column directions in the memory device shown in FIG.

FIG. 9 is a block diagram showing a fifth embodiment of a memory device according to the present invention.

10 is a timing chart of row and column direction block write when masking in the data depth direction is performed in the memory device shown in FIG.

FIG. 11 is a block diagram showing a sixth embodiment of a memory device according to the present invention.

FIG. 12 is a timing chart of row and column direction block write when masking is performed in the row and column directions in the memory device shown in FIG. 11.

[Explanation of symbols]

1 row address decoder (row decoder) 1a upper row address decoder (upper row decoder) 1b lower row address decoder (lower row decoder) 2 column address decoder (column decoder) 2a upper row address decoder (upper column decoder) 2b lower row Address decoder (lower-order column decoder) 3 Sense amplifier / I / O controller 4 Memory cell array (memory cell) 5 Color register 6 Data depth direction mask control circuit (mask control circuit) 7 Row direction mask control circuit (mask control circuit) 8 Column direction mask control circuit (mask control circuit)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H04N 5/907 B 7734-5C

Claims (6)

[Claims] 1. A storage unit having memory cells arranged in a matrix, a row address decoding unit for decoding a row address of the storage unit, a column address decoding unit for decoding a column address of the storage unit, and input data. A temporary data storage means for temporarily holding the data; a first data input means for writing input data to a memory cell of the storage means selected by the row address decoding means and the column address decoding means; Second data input means for simultaneously writing the data of the data temporary storage means to the memory cells of the storage means for a plurality of row addresses regardless of several bits, the first data input means and the second data A memory device having a switching means for switching the input means. 2. The memory element according to claim 1, further comprising a data mask means for masking writing of a predetermined bit in a depth direction of data. 3. The memory element according to claim 2, further comprising row direction masking means for masking writing of a predetermined row address in the row direction of the memory array. 4. The memory device according to claim 1, further comprising: third data input means for simultaneously writing the data of the data temporary storage means to a plurality of column addresses regardless of the lower bits of the column address. The second data input means and the third data input means are used together, and data is stored in the memory cells corresponding to a plurality of row addresses and column addresses regardless of the lower-order bits of the row address and the lower-order bits of the column address. Fourth data input means for writing
A memory device comprising: a switching means for switching between the third data input means and the fourth data input means. 5. The memory element according to claim 4, further comprising a data masking unit that masks writing of an arbitrary bit in the depth direction of data. 6. The memory device according to claim 5, wherein row direction masking means for masking writing of a predetermined row address in the row direction of the memory array, and writing of a predetermined address in the column direction of the memory array. A memory device having column-direction masking means for masking.