JPH05114287A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To make a high-speed access to an optional area by designating a start and a stop addresses when the serial data is output or input to a serial access memory part. CONSTITUTION:A column address signal from an address terminal is input to a start address control circuit SAD and a stop address control circuit STC. The output of the circuit SAD is fed to a decoder SAMDCR. A serial access memory part is comprised of registers DR1, DR2, an input/output bus SAMI/ OBUS and a serial sector between the registers and the input/output bus extended in the longitudinal direction. The data is serially input and output between the registers DR1 and DR2 of the sector in accordance with a select signal formed by a decoder SAMDCR. Accordingly, an optional area can be accessed at high speeds through designation of the start and stop addresses.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a technique effective when used in a multiport memory having a random access input / output port and a serial access input / output port.

[0002]

2. Description of the Related Art There is a multiport memory having an input / output port for random access and an input / output port for serial access. Such a multiport memory is
It is widely used as an image memory for displaying characters and graphics on the screen of a display device such as a CRT (cathode ray tube). Regarding such a multi-port memory, there is, for example, “Nikkei Electronics”, pages 243 to 264, dated Mar. 24, 1986, Nikkei McGraw-Hill.

[0003]

On the one hand, the inventor of the present application has proposed that, on the one hand, the multi-port memory is further increased in capacity and speed with the progress of the semiconductor technology, and on the other hand, the image processing technology. With the progress of the above, attention has been paid to the fact that image processing only in a specific area tends to increase in microcomputers and the like such as the multi-window function. The development of a semiconductor memory device having a function capable of serial access has been achieved. An object of the present invention is to provide a semiconductor memory device having a function of performing high-speed serial access to an arbitrary area with a relatively simple structure. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0004]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, it includes a memory array in which memory cells are arranged in a matrix and a serial access storage unit that outputs or inputs data in parallel, and an arbitrary start address and stop address in an output or input operation of serial data to the serial access storage unit. Is specified.

[0005]

According to the above-mentioned means, an arbitrary area can be accessed at high speed by designating both start and stop addresses, so that high-speed processing of the image data becomes possible.

[0006]

1 is a block diagram showing an embodiment of a multiport memory according to the present invention. This figure shows
It is a block diagram expressed functionally of a circuit, and is not particularly limited, but a memory array MARY for random access.
Has a storage capacity of 512 (rows) × 512 (columns) = about 256K. By accessing eight such memory arrays MARY in parallel, color data of × 8 bits is stored as a unit. Therefore, 4 such multi-port memory
By using the individual pieces, it is possible to store color image data of 256 colors with a high resolution such as 1024 × 1024.

The address terminal is composed of 9 bits A0 to A8, and row-related and column-related address signals are input in time series in synchronization with the row address strobe signal RASB and the column address strobe signal CASB. The column address signal is taken into the row address buffer RAB and the column address signal is sent to the column address buffer CAB or the serial address (start address) control circuit SAD.
Is taken into the stop address control circuit STC. The acquisition of such a start address and stop address is realized by a special input mode which will be described later. In the figure, the two blocks are combined to be SAD & ST.
It is expressed as C.

The serial address control unit SAD performs the counting operation in synchronization with the serial clock, using the input column address as an initial value. This count output is supplied to the decoder SAMDCR for serial access.
The serial access storage unit includes data registers DR1 and D
R2 and serial access input / output bus SAMI / OBU
Serial access input / output bus SAMI / OBUS extending vertically with S and data registers DR1 and DR2
It is composed of a serial selector provided between and.
The serial selector is sequentially selected by the selection signal formed by the decoder SAMDCR, and serial input or output of data is performed between the serial selector and the data registers DR1 and DR2.

Transfer gates TG1 and TG2 are provided corresponding to the data registers DR1 and DR2 divided into two as described above, and these transfer gates TG are provided.
Half of the 512 bit lines of the memory array MARY are connected via 1 and TG2. Therefore, random
Access memory array MARY and data register D
Between R1 and DR2, an operation in which data is mutually transferred in parallel in units of 512 bits and a split transfer operation in which half of the data is separately transferred are made possible. That is, in the split transfer operation, for example, the data register D is transferred via the transfer gate TG2.
While performing data transfer to R2, data register D
A serial access operation is performed on R1 and a serial access operation is performed on data register DR2 while data is being transferred to data register DR1 via transfer gate TG1. By alternately performing such operations, continuous high-speed serial access becomes possible.

The serial output circuit SOB is composed of eight unit circuits, and each unit circuit is composed of a main amplifier and a data output buffer. The serial data transmitted through the serial access input / output bus SAMI / OBUS is amplified and output from the serial data terminals SD0 to SD7.

Serial write data input from the serial data terminals SD0 to SD7 is input / output bus S for serial access through the serial input circuit SIB.
It is transmitted to the AMI / OBUS, and is written in each address of the data registers DR1 and DR2 designated by the serial selector.

The address signal fetched in the row address buffer RAB is input to the row decoder RDCR. The row decoder RDCR decodes the input address signal and selects one word line of the memory array MARY. The address signal taken into the column address buffer CAB is inputted into the column decoder CDCR. The column decoder CDCR decodes the input address signal and forms a selection signal for one bit line of the memory array MARY. Although not shown in the figure, the column decoder CDCR is provided with a column switch circuit, and this column switch is switch-controlled by the column selection signal to switch a pair of bit lines to an input / output bus I / OBUS for random access. To connect. A sense amplifier SA is provided on the pair of bit lines of the memory array MARY. The sense amplifier SA amplifies and outputs the stored information of the memory cell appearing on the bit line, and
The memory level is restored to the original level in the memory cell which is about to be lost by the selection operation, and the memory cell is refreshed. In the figure, this sense amplifier SA and the input / output bus I / OBUS for random access are shown as SA & I / OB.
It is represented by one block like US.

The random output circuit OB comprises a main amplifier and an output buffer, and the random input / output bus I / O.
The read signal output to the BUS is amplified and output from the random data terminals RD0 to RD7. The random write data input from the random data terminals RD0 to RD7 is input to the input data control circuit IDC through the random input circuit IB. The input data control circuit IDC performs simple data processing by performing masking, bit through or inversion on the 8-bit input data in bit units according to the contents of the mask register MSR and the color register CLR. The data is transmitted to the random input / output bus I / OBUS and transmitted to the bit line pair of the memory array MARY through the selected column switch circuit. Since one memory cell is selected in the bit line pair by the operation of selecting the word line, writing is performed.

In this embodiment, although not particularly limited, the block write control circuit BWC makes multiple selections of bit lines by invalidating the lower bits of the input column address, and makes the same content for a plurality of bit lines. Performs data write operation. In such a block write operation, the mask data can be masked by the mask data written in the address mask register AMDR. The flash write control circuit simultaneously selects all bit lines and writes the same data. As a result, the contents of the memory array MARY can be cleared and the initial setting can be performed at high speed.

The timing generation circuit TG includes various control signals RASB, CASB, DTB / supplied from external terminals.
It receives the OEB, WEB, DSF, SC and SEB to determine its operation mode, and generates the operation timing signal of the internal circuit in accordance with it. Signal R
ASB is a row address strobe signal, and CAS
B is a column address strobe signal, WEB is a write enable signal, DTB / OEB is a data transfer control signal, SC is a serial clock signal, and SEB is a serial enable signal. Here, a signal with B added means that the low level is set to the active level.

The memory array MARY is constructed by arranging a dynamic memory cell composed of a capacitor for information storage and a MOSFET for address selection in a matrix at the intersection of a pair of bit lines and word lines arranged in parallel. In a dynamic memory cell, the information level stored in the capacitor will be lost over time. The refresh control circuit RFC performs an operation of reading the stored information in the memory cell before it is lost and amplifying it to write it in the original memory cell. That is, the refresh control circuit RFC forms an address signal for the above refresh operation and inputs it to the row address buffer RAB. By this refresh address signal, a row-related address selection operation of the memory array MARY, that is, a word line selection operation and a sense amplifier amplification operation are periodically performed to refresh the memory cells. Therefore, the memory array MAR
Although Y is composed of a dynamic memory cell, it can be handled from the outside in the same manner as a static RAM.

FIG. 3 is a timing chart of an embodiment for explaining the operation of fetching the stop address. In FIG. 1, the address strobe signals RASB and CASB whose low level is activated are shown in FIG.
Different from the above, it is represented by adding an overbar to the alphabets RAS, CAS, etc. that represent signal names according to a general logical notation. This is the same as in FIG. 4 and FIG.
The same applies to the timing diagram of FIG. However, in the description of the present specification, B is added to the signal that sets the low level to the active level as described above.

To distinguish from normal RAM access,
After the column address strobe signal CASB falls to the low level, the row address strobe signal RASB is set to the low level. Then, the write enable signal WE
B is set to low level (hereinafter, simply referred to as CBRS cycle), and DSF signal is set to high level. The address signal input at that time is the stop address (S
It is taken in through the column address buffer CAB as top Add). Then, one shot pulse is generated at the timing after the address signal is determined, and is set in the address register included in the stop address control circuit STC at that timing.

FIG. 4 shows a timing chart of an embodiment for explaining the operation of resetting the fetched stop address. In order to distinguish from the normal RAM access or the set mode, the column address strobe signal CASB is lowered to the low level, the row address strobe signal RASB is set to the low level, and the write enable signal WEB is maintained at the high level (hereinafter, This is simply called a CBRR cycle.) Reset the stop address register.

FIG. 2 is a block diagram of an embodiment of the stop address control circuit and its associated serial address counter. Address counter ACOUNT
T is a binary counter consisting of 9 bits from 0 to 8,
The start address can be specified according to a specific operation mode. Among the outputs of the address counter ACOUNT, serial address signals other than the most significant bit are output through OR gate circuits G1 to G7 (circuit symbols G2 to G6 are omitted). The address signal 8 of the most significant bit is the data register D divided into the above two.
It is used to distinguish between R0 and DR1.

The stop addresses A0 to A7 are taken into the stop address register SAR. That is, the address signal set by the CBRS cycle as described above is held in the register SAR. This register S
The address signal taken into the AR is the CB as described above.
It is cleared by inputting a new stop address in the RS cycle, resetting in the CBRR cycle, or by a one-shot pulse generated when the power is turned off and the power is turned on again.

In this embodiment, the stop address is designated by a factorial of 2, although not particularly limited thereto. For example, if A7 to A0 are set to 00011111, 2 ⁵
= 32. In other words, 0-512
The column address composed of is divided into two as described above and has addresses such as 0 to 255 and 256 to 511.
On the other hand, the stop address 0001
When it is set to 1111, the address of 256 corresponding to the data register DR0 is divided into eight, 31, 63, 95, 1
27, 159, 191, and 223, and the remaining 256 addresses corresponding to the data register DR1 are also similarly divided into eight.

In this embodiment, an arithmetic circuit LU is provided. In this arithmetic circuit LU, for example, A7 to A0 are 0010.
In the case of being erroneously designated as 1111, the upper 1 of the bit set to 0 is invalidated and 000011 is set.
It operates in the same way as when inputting to 11. For the lower bits 0 and 1, it is assumed that specifying a stop address in such a small unit is substantially meaningless.
Handle 00001 as 00000011. The arithmetic circuit LU is provided in the input part of the stop address register SAR, and performs the logical processing as described above on the address signal input through the row address buffer CAB and stores it in the register SAR. May be

Further, the logic circuit LU inverts the above stop address and OR gate circuits G1 to G.
Supply to 7. That is, A7 to A0 is 0001111
If the pattern is 1 then 11100000
Output as. As a result, the upper bits 111 cause the outputs of the OR gate circuits G7 to G5 to be in the full count state of 111 regardless of the outputs 7 to 5 of the address counter ACOUNT. And the lower 5 bits 0000
Output of address counter ACOUNT corresponding to 0
0 is validated and output.

The NAND gate circuits G8 to G11 are circuits for detecting a full count state, and when the outputs of the NAND gate circuits G8 to G10 which receive the output signals passed through the OR gate circuits G1 to G7 are all 0, in other words, When all the outputs of the OR gate circuits G1 to G7 are in the full cant state of 1, the output of the gate circuit G11 becomes 1
become. Since the upper bits are apparently set to 111 by the designation of the stop address, the full count state can be achieved when all the valid lower bits become 1. The NAND gate circuit G12 includes the full count output signal and the split transfer mode signal signal SP.
A signal COUT for switching from the data register DR0 to DR1 or DR1 to DR0 is generated in synchronization with the basic clock SC3P of the BL and SAM units. That is, when the serial access from the data register DR0 is completed by this signal COUT, the highest column address A8
Is switched from 0 to 1 and the serial access from the data register DR1 is started. When the serial access from the data register DR1 ends, the highest column address A8 is switched from 1 to 0 so that the serial access from the data register DR0 is started.

When the stop address is reset by the CBRR cycle, all output signals through the logic circuit LU become 0, and the address counter ACOUNT is reached.
Is directly input to the full count detection circuit including the NAND gate circuits G8 to G11 and the like, and the full address split transfer mode is executed.

FIG. 5 is a timing diagram showing an example of serial read operation in the split transfer mode. The row address Row is fetched in synchronization with the low level of the row address strobe signal RASB, and the operation of selecting the word line of the memory array MARY is performed. By the low level of the data transfer signal DTB, the storage information of the memory cell corresponding to the selected word line is transferred to the empty data register DR0 or DR1. During this period, the serial output operation corresponding to the start address Ym in the previous split transfer mode is clock pulse SC.
It is done in sync with. Bi and Bj are full-end or designated stop addresses. That is, in order to change the stop address from Bi to Bj, this serial transfer operation is executed during the serial access in which the CBRS cycle shown in FIG. 3 is omitted in the figure.

The address signal input in synchronization with the low level of the column address strobe signal CASB is taken in as a new start address Yi. The serial transfer by the start address Yi is continuously executed from the cycle next to the stop address Bj corresponding to the start address Ym.

As described above, when a specific rectangular area on the CRT screen is designated, the row address corresponding to the vertical address is designated continuously, and the column address is designated by setting the stop address. The start address may be set one by one in the split transfer mode. As a result, reading or writing can be performed on a certain rectangular area.

The operation and effect obtained from the above embodiment are as follows. That is, (1) it includes a memory array in which memory cells are arranged in a matrix and a serial access storage unit that outputs or inputs data in parallel, and an arbitrary start address in an output or input operation of serial data to the serial access storage unit. By designating the stop address and the stop address, it is possible to access any area at high speed. (2) According to the above (1), it is possible to obtain an effect that high-speed processing of image data can be performed on a certain area such as a window. (3) The memory array and the serial access storage unit divide the stored data corresponding to one word line into halves for parallel transfer, and serially output data from one of the divided serial access storage units. Or, it has a split transfer function that parallel transfer is performed between the other serial access storage unit and the memory array that are divided while input is being performed, and the stop address is enabled during this split transfer operation. By doing so, in combination with the high speed operation of the split transfer operation, it is possible to obtain the effect of enabling the high speed operation of serial access of a certain area to be processed. (4) The stop address is specified by a factorial of 2, and the logical sum circuit forcibly logicalizes the upper address signal invalidated corresponding to the stop address specification with respect to the address signal formed by the address counter. By setting 1 and apparently setting the output of the address counter circuit to the full address state, the full address detection circuit can be used as it is, and the effect that the stop address can be designated and the substantial designation can be canceled with a simple configuration. (5) The stop address is fetched by setting the column address strobe signal to the active level and then setting the row address strobe signal to the active level and the write enable signal to the active level.
And by setting the DSF signal to the active level,
The effect that a special control signal can be dispensed with is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example,
In addition to directly inputting the stop address from the outside, if you want to set only a relatively small number of addresses such as factorial of 2 as described above, register a pattern of multiple stop addresses. In addition, various embodiments such as a method of selecting it by an address passed through a column address buffer or a bit input from a data terminal can be adopted. The stop address designation mode may be performed by providing a dedicated control signal in addition to the CBRS cycle as described above. The memory array may be composed of static memory cells in addition to those using dynamic memory cells as described above. The present invention can be applied to a semiconductor memory device having only a serial access port as well as a device having both a random access port and a serial access port.

[0032]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, it includes a memory array in which memory cells are arranged in a matrix and a serial access storage unit that outputs or inputs data in parallel, and an arbitrary start address and stop address in an output or input operation of serial data to the serial access storage unit. By specifying the above, it is possible to access any area at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a multiport memory according to the present invention.

FIG. 2 is a block diagram showing an embodiment of a stop address control circuit and a serial address counter related thereto.

FIG. 3 is a timing chart showing an embodiment for explaining a stop address fetch operation.

FIG. 4 is a timing diagram showing an embodiment for explaining an operation of resetting a fetched stop address.

FIG. 5 is a timing chart for explaining an example of a serial read operation in a split transfer mode.

[Explanation of symbols]

CAB ... column address buffer, RAB ... row address buffer, RFC ... refresh control circuit, CDCR
... column address decoder, RDCR ... row address decoder, MARY ... memory array, SA ... sense amplifier, I / OBUS ... random access input / output bus, F
WC ... Flash write control circuit, BWC ... Block write control circuit, AMSR ... Address mask register, M
SR ... Mask register, CLR ... Color register, IB
... random access input buffer, OB ... random access output buffer, TG1, TG2 ... transfer gate,
DR1, DR2 ... Data register, SAMI / OBUS
... serial access input / output bus, SAMDCR ... serial access decoder, SOB ... serial access output buffer, SIB ... serial access input buffer, SAD ... start address control circuit, STC ... stop address control circuit, TG ... timing control circuit ..

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 27/10 481 8728-4M

Claims (5)

[Claims] 1. A memory array in which memory cells are arranged in a matrix, a serial access storage unit that outputs or inputs data in parallel with the memory array, and an operation of outputting or inputting serial data from the serial access storage unit. A semiconductor memory device comprising: a control circuit for designating an arbitrary start address and stop address. 2. The memory array and the serial access storage unit divide the storage data corresponding to one word line into halves for parallel transfer, and transfer data from one of the divided serial access storage units. 2. The semiconductor memory device according to claim 1, further comprising a split transfer function in which parallel transfer is performed between the other serial access storage unit and the memory array which are divided while serial output or input is being performed. .. 3. A stop address is designated by a factorial of 2, and a logical sum circuit forces an upper address signal invalidated in response to the stop address designation to an address signal formed by an address counter. 3. The semiconductor memory device according to claim 1, wherein the output of the address counter circuit is apparently set to a full address state by setting the logic 1 to 1. 4. The stop address is fetched by setting a column address strobe signal to an active level, then setting a row address strobe signal to an active level, and setting a write enable signal and a DSF signal to an active level. 4. The semiconductor memory device according to claim 1, wherein the address is held. 5. The semiconductor memory device according to claim 1, wherein the stop address is validated only during a split transfer operation.