JPH04341994A - Video memory device with serial mask - Google Patents

Abstract

PURPOSE:To partially update serial data bits of video memory in a column direction during a write period. CONSTITUTION:The contents of a serial mask register 121 are inputted from a serial mask input 114 with the same timing as the data being inputted to a serial data port 113. In accordance with the contents of the serial mask register 121, a memory array 101 selects the bit construction of the serial data and controls the execution of the write in. Therefore, the memory cell 101 partially update the contents of a serial data register 106 in a column direction.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video dual port memory device with a serial input terminal, and more particularly to a video memory device with a serial mask that allows video input from the serial terminal to rewrite only a designated portion of the memory. Regarding.

0002

2. Description of the Related Art FIG. 3 shows the configuration of a conventional video dual port memory device having a serial terminal. This dual port memory device has an address port 210 and a timing control signal input port 21 as interfaces.
1, a random data port 212, and a serial data port 213. The main body of the memory is a two-dimensionally arranged memory array 201, and accessing this dual port memory device requires two addresses: a row address indicating the position in the row direction, and a column address in the column direction. be. Therefore, a row address buffer 204 and a row decoder 205 are provided for row addresses, and a column address buffer 202 and a column decoder 203 are provided for column addresses.

Next, a method of accessing the memory device will be described.

(1) Random read/write

0005
] By simultaneously giving a row address and a column address, information at an arbitrary position in the memory cell array 201 can be accessed. Row address is row address buffer 2
04, decoded by the row decoder 205, and supplied to the memory cell array 201.

Further, the column address is latched into a column address buffer 202 and decoded by a column decoder 203. After that, the value of the cell in the memory array 201 determined based on the decoded values of the row decoder 205 and the column decoder 203 is changed to the random data port 2.
12 for read/write access.

The latch timing signals of the row address buffer 204 and the column address buffer 202 are inputted through the timing control signal input port 211.
It is generated by the internal timing generation circuit 209 using strobe signals including S (row address strobe) and CAS (column address strobe).

(2) Serial read/write operation

00
[09] The serial memory cycle is executed by two transfer means described below. The first transfer is performed by memory array 2
01 and the serial data register 206. This transfer specifies the row address of the memory array 201 using the row address buffer 204 and row decoder 205. Therefore, this transfer is performed in a cycle similar to a random read/write cycle.

The second transfer uses serial address counter 208 and serial address decoder 207 to transfer serial data register 206 and serial data port 2.
13. This transfer can be performed in parallel with the random memory cycle because it does not require the circuitry used in the random memory cycle. Transfer is performed in synchronization with clock input from a serial clock terminal (not shown).

Note that in a so-called word-structured memory in which a plurality of bits can be simultaneously accessed to the same address, there are a plurality of memory array 201 parts. Usually, it has a 4-bit or 8-bit configuration.

0012

Problem to be Solved by the Invention The conventional writing using serial port access has a disadvantage in that it is difficult to partially update the contents of the memory in the column direction.

[0013]

[Means for Solving the Problems] The gist of the present invention is to provide at least two first and second serial data ports, one random port, a memory cell array arranged two-dimensionally in a column direction and a row direction, first register means for holding serial data input from the first serial data port in a column direction; and second register means for holding second serial data input at the same timing as the first serial data. and when writing the contents of the first register means to the memory cell, it is possible to instruct bit by bit whether to write or not based on the contents of the data of the second register means.

[0014]

Effect of the Invention When writing data to the serial masked video memory device having the above configuration, a plurality of data bits held by the first register means can be selectively masked based on data bits held by the second register means. ,
Data bits written to memory cells can be partially changed.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIGS. 1-2 are block diagrams of one embodiment of the present invention. In one embodiment, 101 is a 4-bit memory cell array, 102 is a column address buffer, and 103 is a 4-bit memory cell array.
is a column decoder, 104 is a row address buffer, 1
05 is a row decoder, 106 is a serial data register, 107 is a serial address decoder, 108 is a serial address counter, 109 is an internal timing generation circuit, 110 is an address input port, 111 is a timing control signal input port, 112 is a random data port, 1
13 represents a serial data port, 114 represents a serial mask input port, and 121 represents a serial mask register.

Note that since the memory cell array 101 can be accessed in units of 4 bits, n in FIG. 2 is "4".

The operation of the serial masked video memory device according to this embodiment is the same as that of the conventional example except for write access from the serial data port 113. Therefore, only the parts specific to the present invention will be described below.

[Serial write operation]

This embodiment differs from the conventional example in the write operation using the serial data register 106 and serial data port 113. In other words, information on the bit position to be masked is input to the serial mask register 121 from the serial mask input 114 at the same timing as the serial data register 106, and 4 bits are
Writing is masked by a memory cell write signal mask circuit 132 that is a part of the memory array 101 that is used as a word. This memory cell write signal mask circuit 132 uses the contents 133 of the serial mask register 121.
Contents 135 of serial data register 106 based on
Decide whether or not to write. That is, the bits of the serial data register 106 whose content is "0" in the serial mask data 121 supplied from the serial mask input port 114 in response to the memory cell write timing signal 134 are masked from writing by the circuit 132. , memory cell write signal 131
does not occur, and the corresponding bit of the contents of serial data register 106 is not written to memory cell array 101.

In the above embodiment, serial data register 1
06 and the serial mask register 121 constitute a first register means and a second register means, respectively.

As another embodiment of the present invention, an example in which the polarity of the serial mask register 121 is inverted can be considered. In such another embodiment, the bit whose content is “1” in the serial mask data 121 from the serial mask input 114 is masked from writing by the circuit 132, and the corresponding bit in the content of the serial data register 106 is not written to the memory cell array 101. Not written.

[0023]

As described above, by using the serial masked video memory of the present invention, the contents of the memory can be partially updated in the column direction during writing by serial port access.

For example, if the memory device of the present invention is used as a video memory for image compositing, the serial port is used for inputting the image generated in the previous stage (such as a moving image input of a natural image), and the random port is used to perform drawing in graphics processing. In such processing, the update area of serial input can be partially masked and updated.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram illustrating a memory array of one embodiment.

FIG. 3 is a block diagram of a conventional example.

[Explanation of symbols]

101 Memory cell array 102 Column address buffer 103 Column decoder 104 Row address decoder 105 Row decoder 106 Serial data register 107 Serial address decoder 108 Serial address counter 109 Internal timing generation circuit 110 Address input port 111 Timing control signal input port 112 Random data port 113 Serial Data port 114 Serial mask input 121 Serial mask register

Claims (1)

[Claims] 1. At least two first and second serial data ports, one random port, a memory cell array arranged in a two-dimensional state in a column direction and a row direction, and an input from the first serial data port. the first register means for holding serial data input in the column direction; and the second register means holding second serial data input at the same timing as the first serial data; A video memory device with a serial mask, characterized in that when writing the contents of the serial mask into the memory cell, it is possible to instruct whether or not to write in bit units based on the contents of the data of the second register means.