JPS60129786A - Image memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an image memory device, and particularly to an image memory device for displaying a plurality of types of characters (letters, graphics, etc.) at high speed, for example.

[Prior Art] FIG. 1 is a block diagram of an image display system including a conventional image memory device. In the figure, CPLJl and image memory'! 1lf2 and character generator 3 are mutually connected via data bus 4 and address bus 5, respectively. A CPLI (central processing unit) 1 is a device that controls the entire system. Image memory device 1
2 includes only a memory circuit. The character generator 3 is a device that stores the shapes of multiple types of characters in pixel-by-pixel data. By the way, a character generator that stores a relatively small number of characters, for example, a character generator that stores only simple characters such as alphabets, numbers, and katakana, is usually used on a display device. The data can be read out at a display rate of 1, and there is no need to store the data in the -H image memory device 2 for speed conversion, and the data can be displayed directly on a display device (not shown). However, character generators that store data for thousands of large and small kanji, hiragana, mosaic, and other characters are few and far between and can read out data as fast as the current display rate of Totoro display devices. It's expensive. Therefore, in order to display characters on a display device using a character generator that stores such a large amount of character data, it is necessary to
A method is adopted in which character data is once stored in the image memory 2 and then displayed after speed conversion. In other words, when using this type of character generator, in the conventional configuration shown in FIG. It becomes necessary to repeat the process of inserting the data. For example, 16' pixels vertically and 16' pixels horizontally.
Characters made up of pixels are 8 times wider than the data bus 4.
In the case of a bit, in order to transfer all the data for one character from the character generator 3 to the image memory device W2, it is necessary for the character generator 3 to transfer data 532 times, and to transfer the data to the image memory device 2 the same number of times. data writing is required. In other words, 64 access processes are required. Furthermore, when accessing the character generator 3 and the image memory device 2, address calculations are also required the same number of times. In this way, a large amount of time is consumed even when displaying only one character. Therefore, when trying to display many characters on the entire display screen, there is a drawback that it takes an extremely long time from when the CPU 1 issues a display command until all the characters are actually displayed on the display screen. Another disadvantage is that the load on the CPU 1 is heavy and the CPU 1 cannot be used efficiently.

[Summary of the Invention] This invention has been made to eliminate the above-mentioned conventional drawbacks, and includes a character generator provided in an image memory device and character data written directly from the character generator to a memory circuit. It is an object of the present invention to provide an image memory device that can reduce the load on a CPU and display characters on a display screen at high speed.

[Embodiments of the Invention] The present invention will be described in more detail below with reference to embodiments shown in the drawings.

FIG. 2 is a schematic block diagram showing one embodiment of the present invention. In the figure, a CPU 1 and an image memory device 6 are connected by a data bus 4 and an address bus 5. The image memory device 6 includes a memory circuit 7, a character generator 8, address counters 9 and 10, a controller 11, and the like. A data bus 483 and an address bus 5 are connected to address counters 9 and 10 and controller 11. Address counter 9 is for generating an address for reading character data from character generator 8 , and this generated address is given to character generator 8 .

The character generator 8 and the memory circuit 7 are connected by a data bus inside the data memory device @6. Further, the address counter 1O is a counter for generating a character generator address, and this generated address is given to the memory circuit 7.

Further, the controller 1-roller 11 is for controlling the operations of the address counters 9 and 1O and the memory circuit 7, and outputs two control signals 11a and 11b. One control signal, ie, address update command signal 11a, is given to address counters 9 and 10. Address counters 9 and 10' receive this address update command signal 11a.
in response to update the address that occurs. The other control signal, ie, the write command signal 11b, is applied to the memory circuit 7. When the memory circuit 7 is supplied with this write command signal 11b, it is brought into a state in which data can be written.

Next, the operation of the embodiment shown in FIG. 2 will be explained.

First, the CPU 1 outputs address data corresponding to a character to be read from the character generator 8 to the data bus 4. At this time, the address data output from the CPU 1 does not indicate the entire address data of the character generator 8 in which the corresponding character data is stored, but indicates, for example, the address of the first line of the plural lines forming the corresponding character. It is data.

The data indicating the address output to data bus 4 is
The address counter 9 is set. Ma7C10PU1
outputs to the address bus 5 address data indicating where in the memory circuit 7 the character data read from the character generator 8 should be written. The address data output at this time is also output to the above-mentioned data bus 4).Similar to the l-res data, it is determined in which position in the memory circuit 7 the data of the first line of one character should be placed. This is the data shown. address bus 5
The address data output to address counter '1
Sera 1- is set to 0. On the other hand, since the data bus 4 and the address bus 5 are connected to the controller 1, the roller 11 can know that the address data has been set in the address counters 9 and 10, and can output the address data to the address counters 9 and 10. A write command signal °11b is output to the memory circuit 7 in response to the data set. This puts the memory circuit 7 in a state in which data can be written. 7 address counter 9 provides address data set by CPU 1 to character generator 8.

In response, character data at the address t's is read from the character generator 8 and provided to the memory circuit 7. At this time, the address counter 10
The address data set from U1 is given to the memory circuit 7. Therefore, character data is written into the memory circuit 7 at a position corresponding to the address data given from the 7-dress counter 10. When reading and writing of data for one line of 11 characters is completed in this way, controller 11 outputs address update command signal 11a to address counters 9 and 1O. As a result, address counters 9 and 10 are updated and each generates address data for the next line. Therefore, the character data of the next line is read from the character generator 8 and written to the position of the next line in the memory circuit 7. These operations are repeated until writing of the final line of one character is completed.

When writing of one character to the memory circuit 7 is completed, CPLJl outputs the address data of the next character to the data bus 463 and the address bus 5. In this way, a plurality of character data are written into the memory circuit 7 at predetermined positions. The character data written in the memory circuit 7 is provided to a display device (not shown) and displayed at a corresponding position on the display screen.

As mentioned above, according to the embodiment of FIG.
The image memory device i! performs most of the access processing that was previously performed as software processing. Since the access processing is carried out by a hardware circuit provided in the access processing unit 6, the time required for the access processing can be significantly shortened. Moreover, the load on the CPU 1 can be reduced, and the CPLll can be used efficiently.

In addition to the present invention, it is also possible to use a DMA (direct memory access) circuit, for example, as a method in which a part of the access processing performed by the CPU is performed by a hardware circuit. However, the embodiment shown in FIG. 2 is sufficiently effective even for a device using such an MA circuit.

This is because, in a device using a DMA circuit, when data is transferred, the DMA circuit takes possession of the data bus and address bus from the CPLI. In other words, when transferring data by the DMA circuit, C
This is because PU1 cannot use the data bus and address bus, and their effective use is limited. On the other hand, in the embodiment shown in FIG. 2, data is transferred from the character generator 8 to the memory circuit 7 without using the data north 4 and the address bus 5.
Since this is done using an internal dedicated data bus, the problem described in (a) above does not occur. That is, when character data is being transferred from the character generator 8 to the memory circuit 7, cpUl can freely use the data bus 4 and address bus 5.

In the embodiment shown in FIG. 2 described above, the CPU 1 is configured not to directly access the memory circuit 7;
Of course, it is also possible to configure the memory circuit 7 so that it can be accessed directly from U1.

FIG. 3 is a schematic block diagram showing another embodiment of the present invention, and shows an embodiment in which the memory circuit 7 can be accessed directly from the CPU 1.

In the figure, the configuration of this embodiment is as follows except for the following points.
This embodiment is similar to the embodiment shown in FIG. 2, and corresponding parts are given the same references vi@ and their explanations will be omitted. First, in this embodiment, a gate circuit 13 is provided. This gate circuit 1
3 is a circuit for directly connecting or cutting off the data bus 4 to the memory circuit &'87. A multiplexer 15 is also provided in this embodiment. This multiplexer 1
5 is a circuit for switching the bus directly connected to the memory circuit 7 between the bus from the address counter 1O and the address bus 5; Furthermore, a buffer 14 is provided in this embodiment. A data bus 4 and an address bus 5 are connected to this buffer 14. Then, address data output from the CPUI to the data bus 4 and address bus 5 is temporarily stored. This buffer 14 further includes address counters 9 and 10 . A controller 11 is connected, and address data stored in a buffer 14 is given to these circuits.

Next, the operation of the embodiment shown in FIG. 3 will be explained. First, the operation when character data is read from the character generator 8 and written into the memory circuit 7 will be described as in the case of FIG. In this case, the gate circuit 13 cuts off the connection between the memory circuit 7 and the data bus 4. Further, the multiplexer 15 cuts off the connection between the memory circuit 7 and the address bus 5,
Also, the memory circuit 7 and the address counter 1o are connected. As a result, the device shown in FIG. 3 becomes the 21st! ! ! It operates in the same way as the device of 1, and the
The character data is read out from the memory circuit 7 and stored in a predetermined location of the memory circuit 7.

Next, the operation when directly accessing the memory circuit 7 from CPIJl will be explained. In this case, the gate circuit 13 connects the memory circuit 7 and the data bus 4. and,
The daily output terminal of the character generator 8 is brought into a high impedance state, and the connection between the character generator 8 and the memory circuit 7 is substantially cut off. On the other hand, the multiplexer 15 connects the address bus 5 to the memory circuit 7 in place of the address counter 1o, which had been connected to the memory circuit 7 up to that point. By this, CPU
1 can directly access the memory circuit 7 via the data bus 4 and address bus 5.

As mentioned above, in the embodiment shown in FIG. 3, the memory circuit 7 can be directly accessed from the CPU '1, so the image memory device 12 can display images other than the characters stored in the character generator 8 on a display device (not shown). can be displayed. That is, the image memory device 1 of FIG.
2 can also be used as an image memory for so-called graphics display.

In the embodiment shown in FIG. 3, after the address data output from the CPU 1 is temporarily stored in the buffer 7714, the address counters 9 and 10. ” is given to the controller 11, so the write command for address data, that is, character data output from GPU1 is 111g.
&Even if the processing speed is faster than the processing speed within the memory device 11, the image memory device 112 can respond to such a character f-data loading command at i1% speed. others,
It goes without saying that the embodiment shown in FIG. 3 has the same effect as the embodiment shown in FIG.

Note that the gate circuit 13 and! Lunaplexer 15 and buffer 114 do not necessarily need to be provided together; only gate circuit 13 and multiplexer 15 may be provided, or only buffer 14 may be provided.

c. Effect of the invention] As described above, according to the present invention, the conventional central processing unit (
Most of the access processing that was previously performed by CP CI as software I-processing is now performed by the hardware circuit, which significantly shortens the time required for access processing and also reduces the burden on the central processing equipment. It can be reduced. This allows efficient utilization of the C1 central processing unit. Further, according to the present invention, character data is transferred from the character generator to the memory circuit through a dedicated path line inside the image memory device without using the data bus of the external device. Character data can be transferred without occupying the data bus.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an image display system including a conventional image memory device. FIG. 2 is a schematic block diagram showing one embodiment of the present invention. FIG. 3 is a schematic block diagram showing another embodiment of the present invention. In the figure, 1 is CPtJ, /I is a data bus, 5 is an address bus, 6 and 12 are image memory devices, 7 is a memory circuit, 8 is a character generator, 9 and 10 are address counters, 11 is a controller, and 13 is a gate The circuit includes a buffer 14 and a multiplexer 15. Agent Masuo Oiwa

Claims (6)

[Claims] (1) In an image memory device including a memory circuit for storing data of characters to be displayed, a character generator which stores the shapes of characters of the compound am type in pixel unit data;
a first address generating means for sequentially generating addresses for reading data of individual characters; and the first address generating means for generating an address for writing the data read from the character generator hX into the memory circuit marked #. a second address generating means that sequentially generates addresses in synchronization with the character generator h), and a second address generating means that connects the character generator and the memo 1 circuit to generate character data read from the character generator h). And for transferring data to external devices! An image memory device characterized by comprising an internal path line that is not directly connected to a bus. (2) an image memory device that reads character data commanded from the outside from the character generator and writes the successively generated character data to a predetermined position of the memory circuit commanded from the outside; The first address generating means sequentially generates addresses for reading data corresponding to the externally commanded characters from the character generator, and the second address generating means sequentially generates addresses for reading data corresponding to the externally commanded characters from the character generator. 2. The image memory device according to claim 1, wherein addresses are sequentially generated for writing character data to predetermined positions of the memory circuit instructed from the outside. (3) The device according to claim 2, further comprising means for controlling operations of the memory circuit, the first address generating means, and the second address generating means in response to m external commands. Image memory device. (4) The control means, in response to the external command, sets the memory circuit in a writable state, and sequentially updates the addresses generated by the first address generation means and the second address generation means. An image memory device according to claim 3. (5) The device according to any one of claims 2 to 4, further comprising means for temporarily storing commands given to the first address generation means and the second address generation means from the outside. image memory device. (6) The external command is a command C from a central processing unit, and a data bus and an address bus are connected to the central processing unit, and the central processing unit can directly access the memory circuit. further, separating the character generator from the memory circuit, directly connecting the data bus to the memory circuit, and separating the second address generation means from the memory circuit; Claims 2 to 5 further include means for directly connecting the address bus to the memory circuit.
3. The image memory device according to any one of paragraphs.