JPH0443594B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image display device, and more particularly to a display control device that displays a mixture of text, still images, and moving images on a display device.

[Conventional technology]

A function that uses a raster scanning cathode ray tube (hereinafter referred to as CRT) as a display device to display information such as text, figures, images, etc. stored in memory (for example, refresh memory using dynamic memory). is one of the important functions of an image processing device. Conventionally, this type of display control device generally edits information to be displayed on the screen, such as text, figures, and images, in refresh memory.
It is stored and sequentially read out in synchronization with the scanning timing of the CRT, converted to a video signal, and then sent to the CRT.
In this method, the CRT screen is regularly divided into a large number of small sections, and each small section is made to correspond to a character or graphic element. Alternatively, a still image is expressed as a series of characters or graphic elements. Recently, in addition to displaying this type of text and still image information, the display of video information, in which the position on the screen where it should be displayed can be moved arbitrarily in time, has become particularly popular in the field of game devices. requested.

FIG. 4 is a block diagram showing the main parts of a conventional display device that displays a mixture of text, still images, and moving images. With this display device, for example, birds can be seen in the sky,
When displaying the movement of an airplane, etc.,
Landscapes without movement are displayed as still images, and moving objects such as airplanes are expressed as moving images. The part where still images are displayed is the part surrounded by dotted lines in the figure, and there is a refresh memory (hereinafter referred to as video memory) 10 where display data is edited and stored.
2. Consists of a still image address generation circuit 104 and its peripheral circuits. Display data is input and output from a central processing unit (hereinafter referred to as CPU) 101 by addressing the video memory 102 . Still image display data edited and stored in the video memory 102 is sent to the still image address generation circuit 104 in the order in which it is displayed in synchronization with the scanning of the CRT.
The signals are read out sequentially and converted into a serial video signal 111 by the still image data register 103. The part that controls the display of the moving image includes an attribute memory 112 in which attribute information of the moving image shape, such as the display position on the screen and identification information of the displayed figure, is stored, and a shape memory 112 that outputs actual shape data based on the identification information of the displayed figure. It consists of a data memory 113 and peripheral circuits. During the display period, the video search counter 117 specifies an address every time the vertical scan is performed, reads out the contents of the attribute memory 112, and the video detection circuit 115 selects the video figure to be displayed at that position based on the display position information. The corresponding shape data is read out from the shape data memory 113 based on the figure identification information and stored in the buffer memory 114 so as to correspond to the horizontal position specified by the attribute information. Next, the contents of the buffer memory 114 are sequentially read out at a timing synchronized with the scanning system, and the serial video signal 11 is read out by the video data register 116.
It becomes 9. Video signal 119 is still image video signal 1
11 and a mixer 120, and is supplied to the video signal generation circuit 107 and reflected on the display on the CRT 108.

[Problem that the invention seeks to solve]

In the conventional display device described above, it is necessary to configure a still image display system and a video display system separately, and the still image display data and video display data are stored in separate video memories and shared. That is difficult. In addition, peripheral hardware such as a display address generation circuit and a parallel-to-serial conversion shift register is required for both display systems, which increases the number of signal lines, resulting in a fairly large circuit and an inexpensive display control device. cannot be provided.

The present invention stores still image display data and moving image shape data in a single video memory, shares as much of the hardware required for the still image display system and the moving image display system as possible, and achieves inexpensive display control. The purpose is to provide equipment.

[Means for solving problems]

The display control device of the present invention includes a video memory that stores display data for still images and moving images, and a still image control unit that generates a display data address and display position information on the scanning line for the still image to be displayed on the next scanning line. and,
A video control unit that detects a video to be displayed on the next scan line and generates the display data address of the video and display position information on the scan line, and a video control unit that extracts information to be displayed on one scan line and an editing memory for storing pixel data; a means for selectively switching between display data read address designation information of the video memory and pixel data write address designation information of the edit memory in response to detection of a moving image to be displayed; and read data of the video memory. and a means for determining the pixel data stored in the editing memory and the state of video processing and controlling the writing operation to the editing memory and the generation of pixel data. All display data is edited and stored in a distinguishable form without any reservations, and mixed video signals are generated while maintaining display priority among still images, moving images, and moving images.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention. The display control device of the embodiment includes a video memory 2 that stores shape data of a moving image in addition to text and still image display data, and a still image address generation circuit 3 that generates a read address for still image display data.
, a still image position information generation circuit 4 that generates position information on the scanning line of the still image display data, video identification information that indicates the type of video figure, display position information that specifies the position to be displayed, color information, and Attribute memory 5 that stores other attribute information necessary for video display
, a video search counter 6 that generates addresses for sequentially reading attribute information, a video detection circuit 7 that detects a video to be displayed on each scanning line based on the read display position information, and a video search counter 6 that generates addresses for sequentially reading attribute information; a video position information generation circuit 8 that generates display position information;
A video address generation circuit 9 that generates a read address for shape data based on video identification information, and an editing memory 10 that converts display data read from the video memory into data corresponding to video signal output, edits it, and stores it. , an edit memory address control circuit 11 that controls write and read addresses of the edit memory.
and a write control circuit 12 that generates write data to the editing memory, and the read display data in parallel.
A video data register 13 that serially converts and generates serial video data, a scanning signal generation circuit 14 that generates a CRT scan timing signal, and a video data register 13 that generates a signal to drive the CRT based on the serial video data and the scan timing signal. It is composed of a signal generation circuit 15.

The output of the address selection circuit 17 and the data input/output line 30 are connected to the video memory 2.
A memory write signal for instructing a write operation from the CPU 1 and a memory read signal for instructing a read operation are supplied. Similarly, the output of the address selection circuit 19 and the data input/output line 31 are connected to the attribute memory 5 as well. When writing display data and attribute information to the video memory 2 and the video control attribute memory 5, first the address selection circuit 1
In steps 7 and 19, the value of the address bus 32 of the CPU is selected to be transmitted as an addressing signal, and the data input/output lines 30 and 31 are connected to the data bus 33 via data buffers 18 and 20. . The CPU 1 specifies addresses of the video memory 2 and attribute memory 5 through these control lines and writes data therein. Once predetermined display data is stored in each memory, memory access for displaying these data is then started. Usually, the address selection circuit 17 is the still image address generation circuit 3.
Switching control is performed so that the output of is supplied to the video memory 2. At the same time, the memory read signal is activated and the still image display data is read from the video memory 2. The still image address generation circuit 3 updates the display address every time the video memory 2 is read.
The video memory 2 is accessed continuously while updating the display address, and the display data of still images is sequentially read out. This display data is written to the editing memory 1 by selecting the output of the still image position information generating circuit 4 in the editing memory address control circuit 11 and specifying the write address.
Stored at 0. Furthermore, as the display address is updated, the display position of the display data read out from the video memory 2 on the scanning line moves, and the still image position information generating circuit 4 is unable to store the display data of the still image. Update display position information that occurs in conjunction. In this way, by repeatedly accessing the video memory 2 and the editing memory 10, one scanning line worth of still image display data is edited and stored in the editing memory.

On the other hand, in the video control system, the address selection circuit 19
The output of the video search counter 6 is selected as the addressing information of the attribute memory 5, the video attribute information is sequentially read from the attribute memory 5, and the video detection circuit 7 compares the attribute information of the display position with the scanning line information. A moving image figure to be displayed on the next scanning line is detected. When the video detection circuit 7 detects a video to be displayed, the video search counter 6 is suspended from being updated and the detected search address is held, and based on the information read from the attribute memory 5, the video position information generation circuit At step 8, display position information on the scanning line is generated from the display position attribute information, and at a moving image address generation circuit 9, addressing information for the video memory 2 in which the shape pattern of the moving image is stored is generated from the moving image identification information.

Furthermore, updating of the display address and display position of the still image address generation circuit 3 and the still image position information generation circuit 4 is suspended, and the address selection circuit 17 selects the output of the video address generation circuit 9 to transfer the video from the video memory 2. The shape data of the figure is read out, the edit memory address control circuit 11 selects the output of the moving image position information generation circuit 8, and the shape data of the moving figure is stored in the edit memory at the address corresponding to the display position of the moving image.

In this way, moving image shape data is read out from the video memory 2 in response to detection of a moving image to be displayed, edited and stored in the editing memory 10. In addition,
If the moving image detection circuit 7 does not detect a moving image to be displayed, the operation of reading moving image data from the video memory 2 does not occur, and the above-mentioned still image display data reading and editing operation continue.

The editing memory 10 has a capacity to store display data necessary for displaying at least one scanning line, and during a write operation, the editing memory address control circuit 11
Select the output of the still image position information generation circuit 4 or the video position information generation circuit 8 with , and write the write address 34.
The display data read out from the video memory 2 is converted into data corresponding to direct display such as display timing and video signal level, edited, and stored. In addition, during a read operation, the edit memory address control circuit 11 selects the output of the scanning signal generation circuit 14 as the read address 35, and periodically supplies continuous addresses in synchronization with the timing of the video signal to store the edit memory. Read data sequentially. This read data is loaded into the video data register 13 and subjected to parallel-to-serial conversion.
The signal is shifted in synchronization with the dot clock of the display pixel and becomes a serial video signal, which is sent to the CRT 1 via the video signal generation circuit 15 including a video signal amplifier and the like.
6.

As described above, the operation of reading display data of still images and moving images to be displayed on one scanning line from the video memory 2, and the operation of writing them into the editing memory 10,
By repeating the operations of the address selection circuit 17 and the editing memory address control circuit 11 while being controlled by the video detection signal of the video detection circuit 7,
All display data for still images and moving images are edited and stored in the same editing memory. Furthermore, the stored data is read out in synchronization with the scanning line signal to generate a video signal to be supplied to the CRT. By repeating these series of operations, a mixture of still images and moving images is displayed.

Here, when editing and storing the display data read out from the video memory 2 in the editing memory 10, since the display priority is different for still images and moving images, the writing control circuit 12 controls the writing in the editing memory. Control and prioritize signals. In other words, the priority is higher for the one in the foreground, the lower the priority for the still image (background) behind the video shape, and the overlapping part due to the movement of the video is prioritized by overwriting the display data of the video shape. to be displayed. Similar control is required between moving pictures, and overwriting control is performed in accordance with a predetermined priority order. FIG. 2 is a logic circuit diagram of the write control circuit, and the following explanation will be based on this diagram. It is assumed that the information of one pixel stored in the editing memory 10 is composed of 5 bits as shown in FIG. 3, for example. Among the pixel information, the external shape data OL distinguishes between moving picture data and still image data, and is set to "1" when display data of a moving picture figure is written. Pixel data D ₀ ~ _{D 3}
is color information, which is information that is converted into an optical signal such as a CRT color signal. The write control circuit shown in FIG. 2 is composed of two AND gates 50 and 51, one OR gate 52, and an inversion circuit 53. The display information 30 read out from the video memory 2 in the embodiment shown in FIG.
At the same time, the OR gate ₅₂ determines that valid data has been input to any _of the bits of the pixel data _D0 to _D3 . In the device of the embodiment, all pixel data D ₀ to _{D 3} are “0”
This state is interpreted as the absence of display data, that is, transparency without color information, and it is determined that valid data has been stored when some color information is written to the editing memory 10. and gate 50
inputs the moving image processing signal generated when the moving image to be displayed is detected by the moving image detection circuit 7 of the embodiment shown in FIG. It determines that has been written and generates input information for external shape data OL. The inverting circuit 53 inputs the outline data OL output of the editing memory 10 specified by the write address signal 34 of the editing memory address control circuit 11, and outputs a signal indicating that display data of a moving image figure is not yet stored at the address. occurs.
The AND gate 51 inputs the write timing signal of the editing memory in addition to the outputs of the OR gate 52 and the inversion circuit 53, and when the pixel data of the moving image is not already stored and the pixel data to be written is not transparent, Generates write control signals. When writing still image display data, the external shape data OL is checked, and if video data has already been written, the write signal is not activated. Next, when writing video display data, check the external shape data OL in the same way as for still images.
If something with a high priority is written in the video, the write signal is not activated, and if something with a high priority is not written, the write signal is activated and the external shape data OL is input. generate,
Write it to the editing memory together with the pixel data D ₀ to _{D 3} . Here, in the device of the embodiment, as a priority within a video, a high priority is given to a video that can be detected quickly to be displayed as specified by the video search counter 6. If this pixel information is stored, no writing will occur to the editing memory, thereby achieving video priority control.

〔Effect of the invention〕

As explained above, the present invention stores the display data of still images and videos in the same editing memory in the control of displaying a mixture of different display data such as still images and videos. - There is no need to configure peripheral control circuits essential for display, such as serial conversion shift registers, for still image display systems and video display systems separately, realizing a still image and video display control device with minimal hardware. There is an effect that can be achieved.

In addition, in controlling the storage of display data for still images and videos in the editing memory, identification information for each display data is stored in a part of the editing memory, and the identification information is stored in a portion where the display data for still images and videos overlap. Since the display data that has already been stored is used to determine valid display data, it is possible to interrupt the editing process for video figures into the same process for still images. There is no need for inefficient control such as temporary storage of attribute information, and the overall configuration of the device is extremely simple.

Furthermore, the read address information supplied to the editing memory changes continuously in synchronization with the display timing, and is generally not used on display devices.
A dedicated control circuit is not required because the synchronization signals required for timing control of the CRT can be obtained from the outputs of counters and the like used in the part that generates them.

As described above, according to the present invention, it is possible to share the hardware required for a still image display system and a moving image display system, and to provide an inexpensive display control device with a minimum amount of hardware.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.
FIG. 2 is a logic circuit diagram of a write control circuit according to one embodiment, FIG. 3 is a pixel information format of an editing memory according to one embodiment, and FIG. 4 is a block diagram of a conventional display control device. 1,101...CPU, 2,102...Video memory, 3,104...Still image address generation circuit,
4...Still image position information generation circuit, 5,112...
Video attribute memory, 6,117...Movie search counter, 7,115...Movie detection circuit, 8...Movie position information generation circuit, 9...Movie address generation circuit, 10...Editing memory, 11...Editing memory Address control circuit, 12...Write control circuit, 13
...Video data register, 14,105...Scanning signal generation circuit, 15,107...Video signal generation circuit, 16,108...CRT, 17,19,10
6,118...address selection circuit, 18,20...
...Data buffer, 30, 31...Data input/output line, 32...Address bus, 33...Data bus, 34...Write address, 35...Read address, 50, 51...And gate, 52...
...OR gate, 53... Inversion circuit, 103...
Still image data register, 113... Shape data memory, 114... Buffer memory, 116... Video data register, 120... Mixer.

Claims (1)

[Claims] 1. In a display control device that reads still image and moving image display data stored in a video memory and generates a video signal to a display device, the still image display data address corresponding to the next scanning line and the display on the scanning line a still image control unit that generates position information; a video control unit that detects a video to be displayed on the next scanning line from among a plurality of videos and generates a display data address of the video and display position information on the scanning line; an editing memory that extracts information to be displayed on a scanning line and stores it as pixel data of the scanning line; and an editing memory that extracts information to be displayed on a scanning line and stores it as pixel data of the scanning line; and an editing memory that extracts information to be displayed on a scanning line and stores it as pixel data of the scanning line; Means for selecting and supplying read address designation information of the video memory and write address designation information of the editing memory, and determining the display data read from the video memory, the pixel data already stored in the editing memory, and the state of video processing. 1. A display control device comprising means for controlling a writing operation to an editing memory and generation of pixel data to be written, and for displaying still images and moving images in a mixed manner in a predetermined priority order.