JPS6474596A - Multiplex display controller - Google Patents

Multiplex display controller

Info

Publication number
JPS6474596A
JPS6474596A JP62233120A JP23312087A JPS6474596A JP S6474596 A JPS6474596 A JP S6474596A JP 62233120 A JP62233120 A JP 62233120A JP 23312087 A JP23312087 A JP 23312087A JP S6474596 A JPS6474596 A JP S6474596A
Authority
JP
Japan
Prior art keywords
display
memory
information
picture
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62233120A
Other languages
Japanese (ja)
Inventor
Ichirou Kousono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62233120A priority Critical patent/JPS6474596A/en
Publication of JPS6474596A publication Critical patent/JPS6474596A/en
Pending legal-status Critical Current

Links

Landscapes

  • Studio Circuits (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

PURPOSE: To detect specified picture information from display data read out from a display memory, to selectively control writing operation based on the detected result and the state of superscription instruction, and to selectively use the specified picture element information used for the detection as effective color information. CONSTITUTION: A basic picture display position information generation circuit 6 generates display position information on a scanning line on the screen of a CRT. When the display data for a basic screen becomes complete, a multiple picture processing signal is activated and the display operation of a multiple signal is started. An address selection circuit 17 reads out the output of a retrieval counter 9 in order of the attribute information of an attribute memory 3, detects a multiple picture, and performs the write-control 10 of a superscription instruction signal from the memory 3. In the case the display data read out from the display memory 2 is edited in an editing memory 4, prioritization and the control of a display state are performed by the control circuit 10. The data read out from the memory 4 is parallel-serially converted by a video data register 13 and supplied to the CRT 15 through a video generation circuit 14.
JP62233120A 1987-09-16 1987-09-16 Multiplex display controller Pending JPS6474596A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62233120A JPS6474596A (en) 1987-09-16 1987-09-16 Multiplex display controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62233120A JPS6474596A (en) 1987-09-16 1987-09-16 Multiplex display controller

Publications (1)

Publication Number Publication Date
JPS6474596A true JPS6474596A (en) 1989-03-20

Family

ID=16950074

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62233120A Pending JPS6474596A (en) 1987-09-16 1987-09-16 Multiplex display controller

Country Status (1)

Country Link
JP (1) JPS6474596A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5648680A (en) * 1979-09-27 1981-05-01 Ibm Digital data display system
JPS61290486A (en) * 1985-06-18 1986-12-20 日本電気株式会社 Display controller

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5648680A (en) * 1979-09-27 1981-05-01 Ibm Digital data display system
JPS61290486A (en) * 1985-06-18 1986-12-20 日本電気株式会社 Display controller

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