JP2993745B2 - Frame memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame memory used for a color bit map display, and more particularly to a frame memory suitable for an image file apparatus for processing and displaying image data at high speed.

[0002]

2. Description of the Related Art Conventionally, as a method of configuring a frame memory used for a bit map display capable of displaying a color image, two methods of a plane type and a packed pixel type are well known. In the plain type, a plurality of pixels (pixels) in one color plane are accessed in one memory access, and in the packed pixel type, one pixel is accessed.
The data of a plurality of color planes representing one pixel is accessed by one access. These two methods have different orientations depending on what processing is performed on the image data in the memory.

For example, when digitizing color image data with a color image scanner or the like, R, G
Since the original image is scanned for each of the three primary colors B and B and the data is taken in, the plane type is more suitable. When compressing image data in the frame memory and storing it in a large-capacity external storage device such as a magneto-optical disk or magnetic disk, or when transferring data to or from another point, it is usually necessary to consider human visual characteristics. A method of converting color data of three primary colors into luminance and color difference signals and then processing the signals is used,
In such a case, a pixel type frame memory is more convenient because data conversion is performed for each pixel.

For this reason, there is a general-purpose frame memory which is configured so that both a plane type and a pixel type can be accessed, as described in, for example, Japanese Patent Application Laid-Open No. 61-75390. .

[0005]

Recently, with the increase in speed and integration of memory elements and the performance of peripheral devices, high performance, that is, high image quality is also required for bit map displays. Also, for example, the necessity of displaying a natural image by 2 24 (approximately 16.770,000) colors in which the resolution is 1000 × 1000 pixels or more and the color expression is 8 bits each assigned to the three primary colors of R, G, and B is increasing. ing.

[0006] In such a high-performance frame memory, the amount of data to be handled is enormous, so that high-speed processing is an important point. In particular, in order to transmit a large amount of data or record it on an external medium, data compression / decompression processing is indispensable, and it is important to optimize the access time to the frame memory to achieve high speed. It is an issue.

However, the conventional frame memory configuration is insufficient for such high-speed processing. That is, if an attempt is made to construct a memory that can be accessed in both the pixel direction and the plane direction, data is read several times in the other direction at the time of accessing either one, and then data is read and written again in the desired direction. Processing data took extra time. Further, when performing compression processing of image data, data once transferred from a frame memory to a signal processing circuit via a bus is once again sent to an external medium or a transmission path via the same bus, so that the entire system is compressed. The improvement in throughput was hindered.

It is an object of the present invention to achieve two types of memory access of a plane type and a pixel type in a large-capacity frame memory so as not to hinder speeding up of data transfer.

[0009]

According to the present invention, a frame memory has two systems: a system bus for accessing from a CPU or the like on a system, and an image bus for accessing for image compression / expansion processing. An interface to the bus, an address selection circuit and a data selection circuit for switching addresses and data provided from the two buses and the memory control LSI, and a control signal provided from the two buses and the memory control LSI. To
The address selection circuit, the data selection circuit, and a timing signal generation circuit for generating a control signal for a memory element are provided.

[0010]

[Function] LSI for controlling system bus, image bus and memory
When an access request to the memory is generated by each control signal from the CPU, the timing control circuit determines the priority of each unit, and switches which address and data are supplied to the memory element to the address selection circuit and the data selection circuit. Send out signals for The address selection circuit converts the address information from each of the above sections into an address of an actual individual memory element according to each access format at the same time as the selection of the address, and also for generating a signal for selecting the memory element. A part of the address information is sent to the timing control circuit. The data selection circuit converts the bit arrangement of the data of each section according to the access format of each section according to the bit arrangement of each memory element. Thus,
In both the plane type and the pixel type, it is possible to access the frame memory at a high speed from a dedicated bus.

[0011]

Embodiments of the present invention will be described below. FIG. 1 shows a configuration of a frame memory according to the present invention and a method of connecting to a bus.

In FIG. 1, a frame memory 100 is connected to a system bus 7 and an image bus 8, and each of R, G and B image signals for display and a synchronizing signal Sy.
nc is output.

The address selection circuit 1 switches the address signals input from the system address bus 71, the image address bus 81, and the graphic controller 4 in accordance with the output of the timing controller 3, and supplies them to the memory 5. The data selection circuit 2 is connected to the system data bus 72, the image data bus 82, and the graphic controller 4, and is further connected to the memory 5, and switches data output from the memory 5 according to the output of the timing controller 3. The timing controller 3 includes a system control signal bus 73, an image control signal bus 83, control signals from the graphic controller 4 and the system address bus 71, the image address bus 81, and the address selection circuit 1.
, Which determines which part of the system is making an access request to the frame memory by inputting an address signal from the CPU, performs priority arbitration, and outputs control signals to the address selection circuit 1, the data selection circuit 2, and the memory 5. I do. The graphic controller 4 controls a signal for sending image data from the memory 5 to LUTs (look-up tables) 6 a to 6 c and a refresh control of the memory 5 based on a clock signal generated by the clock generation circuit 9. And sends these signals to the address selection circuit 1, the data selection circuit 2, and the timing controller 3. Normally, a dedicated LSI, for example, HD64400 manufactured by Hitachi, is used. The memory 5 has an address input from the address selection circuit 1, a data input and output from the data selection circuit 2, a control signal input from the timing controller 3, and a signal output to the LUTs 6a to 6c. Data read / write, and LUTs 6a to 6
Output display data to c. In the LUTs 6a to 6c, the display data output read from the memory 5 is parallel-to-serial converted, converted into an analog video signal according to a certain conversion rule registered in the LUTs 6a to 6c, and converted into a display (not shown). ). The clock generation circuit 9 generates a clock signal to be supplied to each section of the frame memory and a synchronization signal to be sent to an external display.

Next, a method of accessing a frame memory according to the present invention will be described with reference to FIG.

FIG. 2A shows the logical configuration of the address space of the frame memory in the present embodiment.
In this example, the entire memory space has a data capacity of 1024 pixels each in the horizontal and vertical directions, and a natural image representation of about 16.7 million colors in total with 256 gradations for each color using 8-bit data for each of R, G, and B. Will be described. When accessing the frame memory 100 from the system bus 7, 32
As shown in FIG. 2B, data of four pixels in the horizontal direction is accessed at a time in any one of the R, G, and B color planes using a bit width data bus. Number one
The order of ~ 4 indicates pixels arranged from left to right on the screen. As shown in FIG. 2C, three colors of R, G and B of one pixel are simultaneously accessed from the image bus 8 by a data bus having a 24-bit width.

FIG. 3 is a block diagram showing a detailed configuration of the address selection circuit 1. FIG. 4 shows the logical meaning of the addresses of the frame memory 100 as viewed from the system address bus 71 and the image address bus 81. 22 bits provided from the system address bus 71 and 20 bits provided from the image address bus 81
The remaining bits of the bit address except the lower two bits are added to the multiplexer 11, and the output is applied to the multiplexer 12 together with the address output from the graphic controller 4. The multiplexers 11 and 12 transmit one input address signal to the output side in accordance with the switching signal ADDSW generated by the timing controller 3. As a result, the address selected by the timing controller 3 among the three addresses appears at the output of the multiplexer 12. The remaining 18 bits of the output of the multiplexer 12 excluding the upper 2 bits are input to the multiplexer 13 and the upper 9 bits are output.
The bits and the lower 9 bits are multiplexed and given as a row address and a column address of each memory element constituting the memory 5. The lower two bits of the address of the image address bus 81 and the upper two bits of the output of the multiplexer 12 are sent to the timing controller 3 and used to generate a signal for selecting an individual memory element.

In this way, as shown in FIG. 4, the upper two bits of the address given from the system bus 7 are used to specify the plane to be accessed among the planes of R, G and B colors. The next 10 bits are used to specify the vertical coordinate of the pixel to be accessed. The lower 8 bits are used to specify the horizontal coordinate of the pixel in units of 4 pixels.
The least significant 2 bits are ignored when accessing from the system bus 7. On the other hand, in the address from the image bus 8, the upper 10 bits are used to specify the vertical coordinate of the pixel, and the lower 10 bits are used to specify the horizontal coordinate of the pixel in pixel units.

In this embodiment, the address on the system bus 7 is represented by an 8-bit byte address used in a system having an ordinary microprocessor as a host.
The number of bits ignored when given as a bit or a 32-bit word address is not limited to this.

FIG. 5 shows a detailed configuration of the data selection circuit 2. 3 input from the system data bus 72
The 2-bit data is connected to a 32-bit 3-state bus transceiver 21. The other data input / output of the bus transceiver 21 is the graphic controller 4
, And further connected in parallel to 32-bit 3-state bus transceivers 22, 23, and 24. 2 input from the image data bus 82
The 4-bit data is connected in parallel to one input / output terminal of a 24-bit 3-state bus transceiver 25, 26, 27, 28. The other input / output of the bus transceiver 22 is connected to the bus transceivers 25, 26, 27, 28.
A 32-bit data line MDATAR0-3 connected to an area for storing R data in data input / output of the memory 5 together with 8 bits of each of the other input / output terminals of the memory 5
1 connected. Similarly, the bus transceiver 2
The other input and output of the bus transceiver 25,
A 32-bit data line MDATAG0-31 together with 8 bits of each of the inputs and outputs of 26, 27 and 28
And G and B of the memory 5 through MDATAB0-31
Connected to the data input / output unit. The three-state bus transceivers 21 to 28 are configured by using three to four 8-bit bus transceivers based on general-purpose TTL, or by using three to four three-state bus drivers and latches.

These bus transceivers have two types of control signals coming from the timing controller 3, namely, an enable input EN for turning on and off an output signal, and
The operation is defined by a direction input DIR that determines the data transfer direction. When accessing the memory 5 from the system bus 7, any one of the bus transceiver 21 and the bus transceivers 22 to 24 is enabled, the bus transceivers 25 to 28 are kept disabled, and the graphics controller 4 The data output also becomes high impedance. As a result, 32 bits of data on the system data bus 72 and MDATA
The data arrays of R, G, and B0-31 are equal. When accessing the memory 5 from the graphic controller 4, except that the bus transceiver 21 is disabled, the graphic controller 4 and the
The bit arrangement order on each data line is matched. When accessing from the image data bus 82, the bus transceivers 22, 23, and 24 are disabled, and one of the bus transceivers 25 to 28 selected by the value of the least significant 2 bits of the image address bus 81 is enabled. . In this way, the data of MDATAR, G, and B can be simultaneously accessed from the image data bus 82 with 8 bits each.

FIG. 6 is a diagram showing where each bit on the bus corresponds to which part of the frame memory 100 when viewed from the system data bus 72 and the image data bus 82. The data selection shown in FIG. This is realized by the configuration of the circuit 2. 32 when viewed from the system bus 7
Bit data corresponds to data of adjacent four pixels in any one of the R, G, and B planes.
7 are assigned to pixels 1, 8 to 15 are assigned to pixels 2, 16 to 23 are assigned to pixels 3, and 24 to 31 are assigned to pixels 4.
Here, the numbers 1 to 4 correspond to FIG. Further, when viewed from the image data bus 82, the 24-bit data corresponds to the data of a certain pixel, and bits 0 to 7 are information of the B signal, 7 to 15 are the information of G, and 16 to 23 are the data of the R signal. Is equivalent to

FIG. 7 shows a detailed configuration of a portion for storing R image data in the entire memory 5. In addition,
The other parts, that is, the parts G and B have exactly the same configuration. In FIG. 7, one plane is referred to using eight image multiport memories (hereinafter abbreviated as VRAMs) 51a to 51h. As the VRAM, for example, HM53 of 1 Mbit (512 × 512 × 4) manufactured by Hitachi
4251 or the like can be used. However, in FIG. 5, for convenience of explanation, connection of a serial port portion for sending data to the LUT is omitted. The address signals MADDR0-8 output from the address selection circuit 1 are V
The data is supplied to the RAMs 51a to 51h in parallel. Of the 32 bits of data MDATAR output from the data selection circuit 2, 4 bits from 0 to 3 are connected to the data input / output terminal of the VRAM 51a. Hereinafter, similarly, each VRAM 51b
To h are connected to 4-bit data lines. Control signals RAS (row address strobe), OER (output enable R), and WER (write enable R) generated by the timing controller 3 are commonly provided to the VRAMs 51a to 51h. Further, the four CASs 0 to 3 (column address strobes) are such that CAS0 is stored in VRAMs 51a and 51b,
1 is VRAMs 51c and d, so that a common CAS is given to two VRAMs each.

VRAMs 51a and b, c and d, e
And each pair of f, g, and h contains 8-bit data representing information of four pixels adjacent to each other. In the case of access from the system bus 7 and the graphic controller 4, the CASs 0 to 3 are simultaneously generated by the timing controller 3 as described later, thereby simultaneously accessing the eight VRAMs 51a to 51h. Also, when accessing from the image bus 8, only one CAS corresponding to the pixel address indicated by the two least significant bits of the address of the image address bus 81 is generated, thereby making it possible to access only the data of one pixel. Become.

In order to send the data read from the VRAMs 51a to 51h to the LUTs 6a to 6c, the graphic controller 4 accesses the display transfer by transferring the address of one row of the VRAM to the serial port for display reading. Display transfer access is RAS and CAS
Is given to the VRAM by giving an OE signal at a timing different from the normal read / write access.

In the present embodiment, 1M bits are used for the VRAM. However, the frame memory 100 according to the present invention can be constructed by using a 256-Kbit VRAM.
In this case, the upper address of the address supplied to the 1 Mbit VRAM may be sent to the timing controller 3 as a signal for selecting a memory chip.

FIG. 8 is a block diagram showing a detailed configuration of the timing controller 3. As shown in FIG. Address decode circuit 31
Is a 2-bit address signal indicating the distinction between the R, G and B planes sent from the address selection circuit 1;
An upper bit of the address input from the system address bus 72 and a strobe signal STB input from the system control signal bus 73 are input, and an upper bit of the system address and an access request from the system bus 7 to the frame memory 100 are sent by the strobe signal. RASCAS timing signal generation circuit 35
An access request from system bus 7 is transmitted to CAS signal generation circuit 37. The address signal input from the address selection circuit 1 is decoded to detect which one of the R, G, and B planes the access request is made, and transmits the plane selection information to the WEOE timing generation circuit 36. .

The mode decode circuit 34 interprets a control signal indicating a request for access to the memory 5 from the graphic controller 4 and determines whether the read / write operation is an actual read / write operation from the memory 5 to the LUT 6a for displaying an image.
6c is indicated, or whether the access is for refreshing the memory 5 or not. Then, the determination result is supplied as a control signal to the priority determination circuit 33 and the RASCAS timing generation circuit 35. When the graphic controller 4 directly generates the access request signal for each operation mode separately, the mode decoding circuit 34 can be omitted.

The priority determination circuit 33 outputs the output of the mode decode circuit 34, the access request signal from the address decode circuit 31, the read / write determination signal R / W from the system control signal bus 73, and the strobe from the image control signal bus 83. A signal STB and a read / write discrimination signal R / W are received as inputs, and a control signal ADDRSW to the address selection circuit 1 and a data selection circuit 2 are provided so that a request source having the highest priority can be accessed according to the priority of each unit. Are generated as control signals EN and DIR. The priority may be given, for example, in the descending order, such as display transfer and refresh from the graphic controller 4, read / write from the image bus 8, read / write from the system bus 7, and read / write from the graphic controller 4. First priority for display transfer and refresh
This is to prevent the image output from being disturbed or the data from being damaged when reading / writing data from / to the frame memory.
The setting may be different from the above depending on the use purpose of the entire system including 0.

The RAS CAS generating circuit 35 receives RAS and CA signals at timings suitable for the specifications of the elements used in the memory 5 based on the same inputs as the priority order determining circuit 33.
It generates S, WE, and OE signals and RASCASSW of a control signal supplied to the address selection circuit 1. The RAS is sent directly to each element of the memory 5, and the CAS, WE, and OE are sent to a CAS signal generation circuit 37 and a WEOE timing generation circuit 36, respectively. Further, a control line for indicating the access for the display transfer is also sent to the WEOE timing generation circuit 36.

The WEOE timing generation circuit 36 has a RAS
The WE, OE signal and the display transfer signal from the CAS timing generation circuit 35 and the plane selection signal input from the address decode circuit 31 are input to R, G and B.
Signals WER, WEG, WEB for each plane
OE signals OER, OEG, OEB are generated and sent to the memory 5. In addition, at the time of access from the image bus 8,
Since three planes are simultaneously accessed at the time of display transfer access, three WEs or OEs are simultaneously output. The number of states represented by the 2-bit plane selection signal input from the address selection circuit 1 to the address decoding circuit 31 is 4, which is one more than the actual number of planes. Therefore, when the address of the extra one plane is accessed on the system bus 7, WER, W
EG and WEB are generated at the same time so that the same data can be written to three planes at a time so that monochrome data and color data compressed by dithering or the like can be written and the memory can be cleared at high speed. May be.

The address decode circuit 32 decodes the least significant 2 bits of data from the image address bus 82, obtains a pixel selection signal for selecting one pixel from four adjacent pixels, and outputs this to the CAS signal generation circuit 37. Send to C
The AS signal generation circuit 37 outputs the R
The CAS signal from the ASCAS timing generation circuit 35 and the strobe signal STB from the image control signal bus 83 are input. In the case of an access request from the image bus 8, the four CAs connected to the memory 5 are selected according to the pixel selection signal.
A CAS signal is sent to one of the S lines CAS0 to 3,
In the case of other access requests, the CAS is sent to all CAS0 to CAS3.

In this way, at the time of a read / write access request from the system bus 7 and the graphic controller 4, the four CAS0 to CAS3 signals are simultaneously generated, and WE or O
The plane is selected by E. This makes it possible to execute plane-type access in which data of four adjacent pixels in one plane is accessed at a time.

When accessing from the image bus 8, W
Three Es or OEs are generated simultaneously, and VRAM elements accessible in each plane are selected by CAS0 to CAS3. This makes it possible to perform packed pixel type access in which access is made over three planes in units of one pixel. Further, in the access from the graphic controller 4 to the VRAM for generating data transfer timing for display, three planes are simultaneously accessed.
It can be executed by AS only refresh.
Since the RAS signal is applied to all VRAMs in common, all VRAMs can be refreshed at a time. At this time, the address selection circuit 1 and the data selection circuit 2
In the above, the addresses and data of the system bus 7, the image bus 8, and the graphic controller 4 are converted to match the arrangement on the actual memory elements of the memory 5 according to the access format of each of these parts, and supplied to the memory 5. You.

As described above, according to the present embodiment, it is possible to access the frame memory from the two systems of buses in a plane type or packed pixel type suitable for each processing purpose. It is not necessary to temporarily store data when reading or writing, so that access from both buses can be performed at high speed. In addition, since access selection in pixel units is performed by the CAS signal of the VRAM, and plane selection is performed by WE or OE, for example, the number of signal lines is smaller than that in which all selections are performed by CAS, and the control circuit is simplified. And the substrate area can be reduced.

In the above embodiment, the memory configuration is 1024 pixels in each of horizontal and vertical directions and 8 bits in each of R, G and B. However, the present invention is not limited to these numerical values. The data lengths of the system bus and the image bus are not limited to the above, and the present invention can be applied to other data widths.

[0036]

According to the present invention, in a frame memory used for a color bitmap display, data access can be realized at high speed by both the plain type and packed pixel type access formats.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a frame memory according to an embodiment of the present invention.

FIG. 2 is a logical configuration diagram of a memory plane in the frame memory of FIG. 1;

FIG. 3 is a block diagram illustrating a configuration of an address selection circuit of the frame memory of FIG. 1;

FIG. 4 is a diagram showing a logical meaning of each bit of an address bus in the frame memory of FIG. 1;

FIG. 5 is a block diagram showing a configuration of a data selection circuit of the frame memory of FIG. 1;

FIG. 6 is a diagram showing a correspondence relationship between each bit of a data bus and a memory plane in the frame memory of FIG. 1;

FIG. 7 is a circuit diagram showing a main part of a memory configuration in the frame memory of FIG. 1;

FIG. 8 is a block diagram illustrating a configuration of a timing controller in the frame memory of FIG. 1;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Address selection circuit, 2 ... Data selection circuit, 3 ... Timing controller, 5 ... Memory, 7 ... System bus,
8. Image bus.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-75390 (JP, A) JP-A-1-283593 (JP, A) JP-A-1-128094 (JP, A) JP-A-62 69291 (JP, A) JP-A-60-76790 (JP, A) JP-A-63-52245 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G09G 5/00 G06F 3 / 153 G06T 1/60 G06T 11/00 G09G 5/06

Claims (4)

(57) [Claims] 1. A frame memory having a signal input / output unit to / from a first bus and a signal input / output unit to / from a second bus and having a plurality of color planes. Address information and the second
The address selection means for supplying to the memory device to select the address information provided from the bus, select a data signal line of said first bus data signal line second bus, said memory device Day sending the data from and supplies or the memory device the data to
Data selection means, and a selection key signal of the address selection means and the data selection means and a memory access timing signal from a control signal provided from the first bus and a control signal provided from the second bus. Timing control means , the address selection means and the data selection means,
When performing memory access from the first bus, 1
In a single access period, the plurality of color planes
One or a plurality of pixels within a specific one color plane
, And memory access from the second bus.
When performing access, during one access period,
Data of a single pixel across multiple color planes
Access to each bus address and
A frame memory, wherein data is connected to the memory element . 2. A memory plane selection signal generating means for generating a memory plane selection signal for selecting a specific one from the plurality of color planes, and a plurality of pixels specified by an address given to the memory element To select a specific pixel from
Pixel selection signal generating means for generating a pixel selection signal common to the plurality of color planes, wherein a specific one of the memory elements is selected by the memory plane selection signal and the pixel selection signal. The frame memory according to claim 1, wherein 3. The method according to claim 1, wherein a specific color plane is selected by the memory plane selection signal when accessing from the first bus, and the pixel selection signal is generated so as to select one or more pixels. 3. The memory plane selection signal simultaneously selects a plurality of color planes when accessing from the bus, and the pixel selection signal is generated so as to select a specific one pixel. 4. 2. The frame memory according to 1. 4. The memory plane selection signal generating means according to claim 1 ,
When a specific address section is designated on the first bus,
3. The frame memory according to claim 2, wherein the memory plane selection signal is generated so that the same data is simultaneously written into the plurality of color planes.