JPH0213317B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a CRT display control device, and more particularly, to a raster scan type color display control device.
This invention relates to improvements in CRT display control devices that display desired characters or graphs by connecting a personal computer to the CRT display device.

Recently, personal computers have come to be used in ordinary households.
Then, a color television receiver for home use was installed.
Attempts are being made to connect a CRT display device to a personal computer and display data from the personal computer on a color television receiver.

FIG. 1 is a schematic diagram showing a state in which a conventional personal computer is connected to a color television receiver. In FIG. 1, when data is input from a keyboard 1 into a personal computer 2, the data is processed and a television circuit 31 contains R, G, and B signals for display on a color television receiver 3. The signal is applied to the matrix circuit 32. Then, the R, G, and B signals are applied to the cathode ray tube 33 via the matrix circuit 32, and a desired character or graph is displayed.

By the way, recently microprocessors and
A single-chip CRT controller (for example, Hitachi HD46505S) is used to connect to a CRT display and relatively easily display data on the CRT display.

Figure 2 shows a diagram using the CRT controller described above.
1 is a schematic block diagram of a CRT display control device. Next, the CRT display control device 4 using the CRT controller 42 will be explained with reference to FIG. The CRT controller 42 basically has a screen memory 46 or 4.
Memory address signal for reading data from 8
A function to output MA ₀ to MA ₁₃ , a function to apply horizontal and vertical periods to the CRT display 54, a function to indicate horizontal and vertical retrace periods, a function to display a cursor on the screen of the CRT 54, It also has a function of receiving signals from a light pen (not shown). And this
The CRT controller 42 includes an internal register group, horizontal and vertical timing generation circuits,
The device includes a linear address generator, a cursor control circuit, and a light pen detection circuit. CRT controller 42 is address bus AB
and is connected to the CPU 41 via the data bus DB. The CRT controller 42 operates at a timing synchronized with the clock signal outputted from the oscillation circuit 43 and frequency-divided by the counter 44. That is, the CRT controller 42 provides memory address signals MA ₀ to MA ₁₃ to the multiplexer 45 . In the multiplexer 45
Address signals A ₀ to A ₁₅ are applied from the CPU 41 . Multiplexer 45 selects one of the address signals and applies it to screen memories 46-48.

The screen memories 46 to 48 are provided to individually store R pixel data, G pixel data, and B pixel data, respectively, in order to display color characters or graphs on the CRT display 54. These screen memories 46
For example, if one screen is made up of 320×200 dots, the numbers 48 to 48 are made up of three memories of 8K bytes each. The screen memories 46 to 48 are selected by a decoder 49 that decodes the address signal input via the address AB. The bit-parallel R, G, and B pixel data read out from the screen memories 46 to 48 are converted into bit-serial signals by the parallel-to-serial conversion circuits 50 to 52, and then sent to the video control 53.
given to. In the video control 53
A horizontal synchronization signal and a vertical synchronization signal are provided from the CRT controller 42. Accordingly, the video control 53 supplies bit-serial image data to the CRT display 54 based on the horizontal and vertical synchronizing signals to display desired characters or graphs.

FIG. 3 is a diagram showing a decoded signal output from the decoder 49 shown in FIG. 2. Next, the operation shown in FIG. 2 will be explained with reference to FIG.
When displaying a color image at an arbitrary point on the CRT display 54, it is necessary to provide the R, G, and B pixel data read from the screen memories 46 to 48 to the CRT display 54, and display each pixel data in a superimposed manner. be. To do this, specify a predetermined address in the screen memory 46 to 48, and
Read out G and B pixel data. That is, first, the multiplexer 54 is connected to the address bus AB of the CPU 41.
Switch to the side. Then, the address signal output from the CPU 41 is given to the screen memories 46 to 48. On the other hand, the decoder 49 decodes the select signal "000" which is part of the address signal and selects the R screen memory 46. At this time, screen memories 47 and 48 corresponding to G and B are not selected. Then, the R pixel data output from the CPU 41 via the data bus DB is written into the screen memory 46. Next, the decoder 49
selects the screen memory 47 and writes the G pixel data output from the CPU 41. Further, the decoder 49 selects the screen memory 48 and writes B pixel data therein. More specifically, the screen memories 46 to 48 are constituted by one memory, and for example, addresses 0 to 7999 are R screen memories, addresses 8000 to 15999 are G screen memories, and addresses 16000 to 23999 are B screen memories. If you want to display black on the CRT display 54, write 0 to addresses 0 to 7999, write 0 to addresses 8000 to 15999, and write 0 to addresses 16000 to 23999.

Next, when displaying the data written in the screen memories 46 to 48 on the CRT display 54, the multiplexer 45 is connected to the CRT controller 4.
Switch to side 2. Then, when the decoder 49 selects the screen memory 46 in the same manner as described above,
R pixel data is given to a video control 53 via a parallel-to-serial conversion circuit 50. Subsequently, when the screen memory 47 is selected, G pixel data is provided to the video control 53 via the parallel-to-serial conversion circuit 51. Furthermore, when the screen memory 48 is selected, B pixel data is provided to the video control 53 via the parallel-to-serial conversion circuit 52. and,
The video control 53 receives input R, G, B.
The pixel data of is given to the CRT display 54,
Each pixel data is superimposed to display an image of a desired color.

As mentioned above, in the conventional CRT display control device 4, the screen memories 46 to 48 that store R, G, and B pixel data are individually selected and accessed by the decoder 49, which reduces the processing time. becomes longer and the CPU
There was a problem that the efficiency of 41 was reduced.

Therefore, a primary object of the present invention is to provide a CRT display control device that can increase CPU efficiency by allowing at least two or more screen memories to be accessed simultaneously.

To summarize the invention, an addressing means including three screen memories for storing R, G, and B pixel data and a read-only memory is provided, and an address signal is given to the read-only memory from the address signal generating means. In particular, in response to at least 3
three screen memories individually and at least two screen memories simultaneously; It is configured so that screen memory can be specified at the same time.

The above objects and other objects and features of the present invention will become more apparent from the detailed description given below with reference to the drawings.

FIG. 4 is a schematic block diagram of one embodiment of the invention, and FIG. 5 is a diagram showing a selection signal output from read-only memory (ROM) 55 shown in FIG. 4.

The embodiment shown in FIG. 4 is the same as the embodiment shown in FIG. 2 described above, except for the following points. That is, in the example shown in FIG. 2, one of the screen memories 46 to 48 is individually selected by the decoder 49, but in this embodiment, the ROM is used instead of the decoder 49.
55 will be provided. As shown in FIG.
8 individually, two screen memories at the same time, or three screen memories 46 to 48 at the same time. When accessing each of the screen memories 46 to 48 at the same time, the multiplexer 45 is switched to the CPU 41 side, and an address signal including the select signal "111" is applied from the CPU 41 to the ROM 55. Then,
The ROM 55 outputs selection signals for selecting each of the screen memories 46 to 48 at the same time.
Therefore, the screen memories 46 to 48 are designated with predetermined addresses at the same time, and data output from the CPU 41 is written therein. Screen memory 46 to 4
When reading data from ROM 8, switch the multiplexer 45 to the CRT controller 42 side,
55 outputs a selection signal for simultaneously specifying each of the screen memories 46 to 48. As a result, R, G, B
pixel data are read out simultaneously.

As described above, according to the present invention, at least three screen memories are designated individually or at least two screen memories are designated simultaneously based on the data stored in the read-only memory. The time required to access memory can be shortened.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing a state in which a conventional personal computer is connected to a color television receiver. FIG. 2 is a schematic block diagram of a conventional CRT display control device. FIG. 3 is a diagram showing a selection signal output from the decoder shown in FIG. 2. FIG. 4 is a schematic block diagram of one embodiment of the present invention. Figure 5 is shown in Figure 4.
FIG. 3 is a diagram showing a selection signal output from a ROM. In the figure, 41 is a CPU, 42 is a CRT controller, 45 is a multiplexer, 46 to 48
is a screen memory, 50 to 52 are parallel to serial conversion circuits,
53 is a video control, 54 is a CRT display, and 55 is a ROM.

Claims (1)

[Claims] 1. A CRT that displays a desired image by giving R, G, and B pixel data to a color CRT display.
In the display control device, at least three screen memories each individually storing the R pixel data, G pixel data, and B pixel data, address signal generating means for generating an address signal, and the address signal generating means. A lead for storing in advance data for individually specifying each of the at least three screen memories and data for simultaneously specifying at least two of the at least three screen memories in response to the means output. A CRT display control device with addressing means that includes only memory.