JPS5936291A - Crt display controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a CRT display control 14U, and more particularly, to a CRT display control 14U that displays a desired character or graph by integrating a personal computer 1a into a raster-type color CR1 display.
This invention relates to an improvement in a display device I-CJ-) and scissors d.

Recently, part-norm computers have come into use in ordinary households.

Attempts are now being made to connect a home color television receiver to a personal computer as a 01 display KM and display data from the personal computer on the color television receiver.

FIG. 1 is a schematic diagram showing a conventional personal computer connected to a color television receiver. 1st
In the figure, when the data entered from the keyboard is entered into the personal computer 2, the data is processed and displayed on the color television receiver 3. The signal is given to a matrix circuit 32 included in a television circuit 31.The R, G, and B signals are sent to a cathode ray tube 33 via a C17 matrix circuit 32.
is given, and the desired Gitractor or graph is displayed.

By the way, recently Micropro L Tsuza and 0R-r T
In order to display the data on the Cf71 Ice Play for comparison purposes, the Cf71 CRT is connected to the Cf71 Ice Play. 46505 S) is used.

Figure 2 shows CR1 using the above-mentioned CR'r control C'-ra.
FIG. 4 is a schematic block diagram of the display control [4]. Next, refer to Figure 2.
The CRT ice play control device 4 using CRT 2 will be explained below. The CR controller 1-roller 42 basically has the function of outputting memory address signals MAo to h-IA+x for reading data from the screen menus 46 to 48, and the function of outputting the memory address signals MAo to h-IA+x for reading data from the screen menus 46 to 48, and the function of outputting the horizontal signals J3 to the CRT display 54.
In addition, there is a function to display the horizontal line J3 and the vertical retrace line 1111, a function to display the cursor on the screen 1f11 of the CRT 54, and a function to display the cursor on the screen 1f11 of the CRT 54.
~The function of receiving 18 months from the pen (shown L!+J'') is on the right.Then -C1 this CF<1-commill roller/'I2 is the internal register l;r and the horizontal 1jIttl
Jj and vertical timing generation circuits, linear address generators, cursor control circuits, and line 1 to
The pen detection circuit is configured to include a pen detection circuit. The CRT controller 42 is connected to the CPU 41 via an address bus A[3Jj J and a data bus DB. And C.R.
The T controller 42 achieves its operation at a timing synchronized with a clock signal outputted from the oscillation circuit 43 and frequency-divided by the counter 44. In addition, CRT controller 1 to roller 42 receive memory address signals MAo to MA+3.
is applied to the multiplexer 45. Address signals AO to Ass are applied to the multiplexer 45 from the CPU 41. The multiplexer 45 selects one of the addresses f,
Select IR=3 and apply it to screen memories 46-48.

Screen memory 46-48 is CR1-display (
5/I It is designed to individually store R pixel data, G pixel data, 13 pixel data, etc. in order to display color tractors or graphs. It will be done. These screen memories 46 or 4ε)
If one screen is made up of 320 x 200 dots, then 4'l is created by the three squares of 81 bytes each! will be accomplished. Zoshi C1 picture mask [Su46 or
181; The address signal inputted via the L address bus AF34 is selected by the decoder/I9. The pit/parallel R, G, [3 The pixel data 5' 1. is transferred to the parallel-to-serial conversion circuit 50/j: to the serial signal 52, and is applied to the video controller 1 to roll 53.
It will be done. 1. CR
T:] A horizontal synchronizing signal and a superimposed/direction same 1st signal are given from the 42.
ml nl-'l-le 531.i water XI' Ji yo(
J'ffl Direct RI ItlJ Gg Lj on the moon-
(Create the image data of the bit center column CR'1-7-Ispray 54 L: Lj and select the desired main 11 characters or 1.
Display graphs, etc.

FIG. 3 is a diagram illustrating the JL data output from the decoder 49 in accordance with FIG. Next, the operation shown in FIG. 2 will be explained with reference to FIG. CR1 display 5
/'If you want to display a color image at any point on I, you can display it on the screen from /16 to 48. ! I water data CR1 de, r spray 4! l)
In addition to 4, there is 8, in which each pixel data is combined and displayed. For this purpose, a predetermined address in the screen memory 46 or 4/3 is specified and l'? ,G.

13 li! iI water data All data is 0, but first, multiplexer 45 is connected to CI) U 711 address bus A.
There are 11 units on the B side. Rirudo, C; P tJ /I
The address signal output from 1 is applied to screen menus 46 to 4B. On the other hand, the encoder 49 decodes select number 1j r000J, which is part of the address signal, and decodes the R screen memory 464! :3M selection is overturned. This place,
Screen memories 47a3 and 48 corresponding to Od3 and B are selected IL! Not done. Then, the pixel data of 1 (1) outputted from the CPU 41 via the data bus DI3 is output to the screen memory 46. Next, the decoder 49 selects the screen memory 47 and Input and output pixel data.Roughly speaking, the decoder 49 inputs and outputs pixel data from the screen memory 48.
Select to import the 1IiIl water data of B. J: To explain specifically, screen memory 46 to ll 8 to 1
For example, 1 screen memory has addresses 0 to 7999, and 8000 to 1599
9 address is G screen memory, 16000 to 2
3999 address is 8 screen mail Ritozu, CRI-
If you want to display black on the display 54, add an O to the address 0 to 7999 and enter the address 8000 to 159.
Write 0 to/from 99 and write 0 to 16000 to 23999.

Next, when the data written in the screen memories 46 to 48 is to be displayed on the CRT display 54, the multiplexer 45 is switched to the CRT controller 42 side.

Then, in the same manner as described above, when the decoder 49 selects the screen memory 46, the R picture '1fi51'''-1 is given to the video control 53 via the parallel-to-serial conversion circuit 50.Subsequently, the screen When memory 47 is selected, O
pixel data is given to the video control 53 via the parallel-to-serial conversion circuit 51. Further, when the screen memory 48 is selected, the B pixel data is given to the dode A control 53 via the parallel-to-serial conversion circuit 52. Then, the video controller 1-〇-rule 53 receives the input R and G signals.

The pixel data of B is given to the CR [eye display 54, and each pixel data is superimposed and an image of a desired color is displayed.

As shown in J-E above, in the conventional CRT display control device 4, the screen memories 46 to 718 that store R, G, and B pixel data are individually selected and accessed by the decoder 49. However, there are problems in that the processing time becomes long and the efficiency of the CPU 41 decreases.

Therefore, the main purpose of this invention is to reduce the screen memory so that two J's F can be used at the same time. ('; P (C) which can increase the efficiency of
The purpose of this invention is to provide an RT5'' display control device.

To summarize, this invention can be used to convert each R, G, and B pixel data into 6 pixels.
[: Memorize the three screen memories a+pu, address Mizuki R
(In response to the message given by the cow means, / < 1 address of at least 3 screen memories and at least 2 screen memories. !
An addressing means fixed for 1 h is installed at f.

The purpose and features of this invention are described below with reference to Figure 1.
It will become even clearer in the future.

Figure 4 is the fruit of this invention bI! This is a schematic block diagram of the i example, and is a schematic block diagram of the example shown in Figure 5 (, ↓).
RC1,I) 5! 5 is a diagram that does not show a selection signal outputted from 5 to 1; FIG.

The embodiment shown in FIG. 71 is the same as g 2 Ull and ff1J described above except for the points below. ! J-<14)
15, k'52 If<l ni tj' example is T2]
In this embodiment, a ROM 55 is provided in place of the decoder 49. R.O.
As shown in FIG. 5, M55 can select one of the screen memories 46 to 48 individually according to the select signal, select two screen memories simultaneously, or select three screen memories simultaneously.
It is preprogrammed so that two screen memories 46 to 48 can be selected simultaneously. And screen memory 46
When accessing each of 48 to 48 at the same time,
Multiplexer 45 as c p U 4. Switching to the i side, the CPU 41 gives an address signal including the select signal r111J to the ROM 55. Then, the ROM 55 outputs a selection signal for selecting each of the screen memories 46 to 48 at the same time. Therefore, the screen memory 46
48 are designated at the same time by a predetermined address, and the CPU
Write the data output from 41. When reading data from the screen memories 46 to 48, the multiplexer 45 is switched to the CRT controller 42 side, and the ROM 55
li′i1 from each of the screen memories 46 to 48
Outputs a selection signal for specifying the time.

The binding is R, G from screen number 716 to 48.

B's landscape data will be published at llil time.

As described above (J, according to the present invention, there are at least three screen menus and at least two screen menus:
By specifying 1 node to 11, γ, the time required to access the screen can be shortened.

[Brief explanation of the drawing]

Figure 1 shows a state in which a conventional personal computer is connected to a 7J large television receiver.
1) - There is a block diagram C of the tool unit U. Figure 4 is a diagram showing the selection signal output from the controller shown in Figure 2. FIG. 5 is a diagram showing the selection 11V+ signal outputted from the ROM shown in FIG. 4. FIG. is CRT=
1in i~1]-ra, 45 is an input screen, 46 to 48 are screen screens, 50 to 52 are parallel to serial conversion circuits,
53 is I:,')-o'ntrol; U4 is CR'I
-'r'chair 7L/I', 55 indicates ROM. Special 6'F Applicant Shitoip Co., Ltd. (and 2 others) 1 Figure 1-:: 1 Figure 3

Claims (2)

[Claims] (1) R and G on color CRT display. Change the water measurement rate of B) and display the desired imageC.
At least three screen memories, each of which individually stores the R pixel data, G pixel data, and 8 pixel data, generate an address signal. - address 1g yen generation means. 011 display computer 1-a-, comprising address specifying means for simultaneously specifying the addresses of at least two of the at least three screen memories in response to the output of the address signal generating means in J3 and ^(I) device. (2) Address specifying means 1, data for individually specifying each of the at least three screen memories and data for simultaneously specifying at least two of the at least three screen memories. Please write it down in advance! The CR "display control device" according to claim 11, comprising a read-only memory.