JPS6288473A - Memory access device - Google Patents

Abstract

PURPOSE:To fetch a series of data at a relatively high speed against the access time of a memory, by circularly writing the series of data in plural memories and circularly reading out the data. CONSTITUTION:Data from a CD-ROM driving unit (CPU)1 are once stored in a buffer memory 23 through an input data bus 20. The input data fetched from the buffer memory 23 are distributed to a pair of data buses 21 and 22 by a distributor 24 and sent to a data control section 10 and RAMs 31-36. Write enable signals WE1-WE6 and a raw address strobe signal RAS are added to the RAMs 31-36 from an address control section 41 also supplies a column address strobe signal CAS and output enable signal OE to the pairs of the RAMs 31 and 34, 32 and 35, and 33 and 36.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Field of industrial application B. Overview of the invention C. Prior art D. Problem to be solved by the invention E. Means for solving the problem (Fig. 1) F. Effect G. Example G1. Configuration (Fig. 1) 02 Write operation in normal display mode P (FIGS. 1 to 3) G3 Read operation in normal display mode (FIG. 1).

Figures 3 and 4) 04 Writing operation in double density display mode (Figures 1 and 5)
(Fig. 6) Readout operation in G5 double density display mode (Fig. 1, Fig. 6)
(FIG. 7) Effect A of the Invention Industrial Application Field The present invention relates to a memory access device suitable for image data processing.

B. Summary of the Invention The present invention makes it possible to sequentially read a series of data at a relatively high speed relative to the memory access time by cyclically writing a series of data into a plurality of memories and reading the data cyclically. This is how it was done.

C Conventional technology Recently, digital processing of video signals has improved the precision and reproducibility of processing,
It has become widely used due to its flexibility.

In this case, in order to temporarily store a large amount of image data, an IC image memory such as a large-capacity dynamic RAM (r) RAM) is used.

D Problems to be Solved by the Invention For example, in a screen with 512 dots horizontally and 256 lines vertically, the total number of dots on one screen exceeds 130,000. When this screen is read out at a standard speed of 60 frames per second, the readout time per dot is about 100 nanoseconds.

However, the access time of currently available DRAMs is, for example, a maximum of 75 nanoseconds, which does not have enough margin for the above-mentioned read time of 100 nanoseconds per dot. However, even if the DRAM is used in R-ge mode where the row address is fixed and the column address is changed, there is a problem in that it is difficult to read out the data of each dot continuously.

Furthermore, for example, a screen has a display density of 512 lines and 512 dots both vertically and horizontally, which is twice the display density of the above-mentioned screen.

Since the read time per dot is as short as about 50 nanoseconds, there is a problem in that commonly available DRAMs cannot be used as they are.

In view of this, an object of the present invention is to provide a memory access device that can sequentially read a series of data at a relatively high speed relative to the access time of the memory used.

E. Means for Solving Problems The present invention is provided with a write control means and a read control means for respectively controlling writing and reading of a number of memories, and the write control means sequentially circulates a series of data in a plurality of memories. Write exactly.

The read control means is a memory access device that sequentially and cyclically reads out a series of data from a plurality of memories at predetermined intervals that are relatively fast with respect to the access time of the memories.

F Effect According to this configuration, a series of data is sequentially read out at a relatively high speed relative to the access time of the memory used.

G. Embodiment An embodiment of a memory access device according to the present invention will be described below with reference to the drawings.

G1 configuration The configuration of one embodiment of the present invention is shown in FIG.

In Figure 1, (1) is a CD-ROM drive unit (CDU), which is a well-known music controller. A CD that has still image data, graphics data, etc. recorded on an optical disc similar to an optical disc (CD).
ROM is installed.

In this example, these data are as follows.

The data has been subjected to appropriate compression processing, and for example, one set of two 8-bit chromaticity data and four luminance data corresponds to four pixels (dots). .

01 is a data control unit, which has first and second register groups (1η and 0).Both register groups 01 and 02
are each composed of six registers (lla) to (llf) and (12m) to (12f).

(7), 0! Yu and (b) are each data buses.

The image data from the CDU is temporarily stored in the buffer memory (E) via the input data path (E).

The input data taken from the buffer memory (e) is as follows.

A pair of data buses Qη and (A) are connected by the distributor (C).
The 8-car data buses (c) and (a) distributed to are connected to the data control unit (10).

09 to (b) are respectively dynamic RAMs,
The first to third RAMs (3]) to OI are connected to the first data bus (c), and the fourth to sixth RAMs (34 to (
to ) is connected to ) to the second data path. Each RAM
@t)~OQ is, for example, 256 human DRAM 2
Consists of individuals.

0υ is an address control unit, which functions as the central processing unit (CPU) of the computer. Data is supplied to the address control unit @p from CDTI (1) via input data path 1, and CP[JH is Data bus (branch): Connected to. Clock CLK and operation mode signal order are supplied from address control unit 0 to data control unit 0 (1).

The address signal BA and the write/read control signal WA are supplied to the buffer memory (A), and the 1 distributor (A) is supplied with the address signal BA and the write/read control signal WA.
The distribution control signal DB is supplied to c).

Note that the data bus structure as described above makes it possible to reduce the number of connection points between the data control section α1 and each of the RAMs 01) to (b).

Furthermore, under the control of the CPU @J, the address control unit 1 (
For the first to sixth RAMs 01 to (g),
The following signals for each food are supplied respectively.

That is, the first to sixth write enable signal sections 1 to WE6
are supplied to each RAM C1tl~(b), and a row address strobe signal RAS is supplied to each RAM C1tl~(b), respectively.
AM (3) to (b) are commonly supplied. In addition, the first and fourth RAM @1) and (b), the second and fifth RAM
RAM O and oi and 3rd and 6th RAM
((:l and (b) are each a pair, and one set of first to third column address strobe signals and output enable signals for each pair CAB 1 and OEI
, CA32 and OH2 and CAB 3 and OH2
are supplied respectively. Furthermore, the first to third RAM H
A first address signal ADI is commonly supplied to the RAMs 1 to 2, and a second address signal AD2 is commonly supplied to the fourth to sixth RAMs (b) to (b). Note that in the operation mode described later, the five address signals are shared.

The data control unit 00 outputs data for three glazes corresponding to the three primary color signals of red, green, and blue, and the address control unit (G) outputs horizontal and vertical synchronization signals. The image is displayed on the omitted image display section. The display density is 1 in normal display mode, for example, the height is 256
The horizontal line is 512 dots, and in double density display mode, for example, 1 vertical dot.

Both sides have 512 lines and 512 dots.

02 Write Operation in Normal Display Mode Next, a write operation in the normal display mode according to an embodiment of the present invention will be described with reference to FIGS. 2 and 3.

In the normal display mode, the 1 distributor (c) is controlled by the distribution control signal D8 from the address control section @η.

Any one of the first to third RAMs (3) or the fourth to sixth RAM (14 to (g)) is used, for example, 9.5MHI as shown in Figure 2. One division is four times the period To of the clock CLK of repetition frequency,
Data is transferred from the buffer memory.

That is, as shown in FIG. 2B, at time t0, the horizontal Okasuke signal falls, coinciding with the rise of clock CLK, and at time t, which is delayed by one clock period T6 from this time t0,
, a row address strobe signal RA8 as shown in FIG.
At time t2, which is further delayed by T0 from time t1, a column address strobe signal CAB as shown in the figure is commonly supplied to RAM H~ (to).
Both straws! Signals RAS and CAS change from time t2 to Tc
It is cut off at time t5, delayed by one.

Time t. During the period -15, the address of the buffer memory is set to the row and column J, as shown in E of the figure.

On the other hand, the addresses of RAM (31) to (c) are shown in the figure F.
As shown in the figure, there are m rows near time t1, and n columns near time t2.

During the period from time t to t5, the output enable signal BOE as shown in FIG. The first pig d0 is taken out to the first data bus e1 via the distributor (c).

On the other hand, during the period from time t to t3, the first RAM 01 is supplied with the first write enable signal 1 as shown in J in the figure from the address control unit 01, and the first write enable signal 1 as shown in FIG. The th data d0 is written into the first RAM 0.

After time t, as shown in FIG.
The first transfer cycle PTI ends at time t4, which is delayed by one clock cycle T0.

In the second transfer period PT2, as shown in FIG.
Is the th data d1 a data bus? ■The second write enable signal type 2 is taken out from the address control unit θ.
is written to the address of the m row and n column of the second RAM p@.

Similarly, in the third transfer period PT3,
As shown in , the third data d2 extracted from the address in the first row and column (j+2) of the buffer memory
The third RAM
(3: Written to the address of lOm row and n column.

Furthermore, in the fourth to sixth transfer cycles PT4 to PT6, as shown in FIG. -6th data d3 to d5 are extracted.

The first to third write enable signals ■1 to ■3 cause the first to third RAMs (m rows of 3η to 01, respectively)
(n+1) column addresses sequentially.

Thereafter, a series of data is sequentially and cyclically written into the first to third RAMs (+1) to 01 in the same manner as shown in FIG.

03 Readout Operation in Normal Display Mode Next, the readout operation in the normal display mode of this embodiment will be explained with reference to FIG.

As shown in FIG. 4A, the timing t-1 coincides with the rising edge of the clock CLK having a repetition frequency of, for example, 9.5 MHz.
In this case, a row address strobe signal RAS as shown in FIG.
((1) to 0]), and as shown in FIG. F, the row address of each RAM (31) to 01 is fixed to m rows.

At time t0, which is delayed l clock period T0 from time 1-, the first column address strobe signal CAR1 as shown in FIG.
Supplied to CII. W clock period T from time t0,
At time t1 delayed by /2, the second
The column address strobe signal CA82 is supplied from the address control unit θp to the second RAM O'J, and at a time t2 delayed by T,/2 from the time t1, a third column address as shown in FIG. A strobe signal CA33 is supplied to the third RAM ((lK). By supplying these column address strobe signals CAJ, CA32 and CA33, access to each RAM O→, 0'4 and (to) is started. .

As shown in FIG. 4 C-FK, each supply start time point 10.1 of CA31, CA32, and CA33. And in C2, the addresses of RAM 61, 0'4, and 01 are all m rows and n columns, and as described above, each address is data d. .

d and d2 are written.

Each supply time t of the signals CA31, CAB2 and CA33. .

Time 1. Delayed by lock period T, /2 from tl and C2, respectively. , 1. and tl, as shown in G, H and JK of the same figure, the first. Second and third output enable signals OEI, OF2 and OF2 are supplied from the address control unit @ to each RAM H*02 and (to), respectively. Then, as shown in K in the same figure, C
A31, CA32 and CA33 supply point 'o t
Approximately 3T1 from '1 and C2 respectively. After a delay of /4 access time, data d0.d and d2 are sequentially read out from each RAM well 0''4 and (to). Three registers of C1 (l1m)
, (llb) and (lie), respectively.

Time t when each column address strobe signal is first supplied
0. 2Tc each from tl and C2! At time points 14.15 and C6 when the address is delayed, the table column address strobe signals CA31°CA32 are activated as shown in FIG. 4C, D and E.
and CA33 from address control unit 09 to each RAM C1
Re-supplied to terminals 0'4 and 0 terminals. At this time, each RA
The address for M6 is as shown in F of the same figure.
Both have m rows and (n+1) columns, and as mentioned above, these addresses have data d, d, and d, respectively.
is written.

Re-supply of signals CA31, CA32 and CAB3 at time t4. At time points t5, t4, and t7, which are clock periods T and /2 older than C4 and C6, respectively, as shown in FIG.

Pressure as shown in H and J, 1st. The second and third output enable signals OEI, OF2 and OF2 are sent from the address control unit @η to each RAM (3◇, 0 and 01
each will be supplied again. Then, as shown in figure K, time 10.1. Data dS, d4, and d5 are sequentially read out from each RAM H, e3→, and (to) after an access time of 1 and t2, respectively. These data d, , d4 and d6 are connected to the data bus Qυ
The three registers (lld) of the data control unit (g) are
), (11.) and (llf), respectively.

In this way, six pieces of image data d corresponding to one set of four faces
0 to d5 are read. Thereafter, a series of image data is sequentially and cyclically read out from RAM01 to RAM01, with four periods of the clock signal CLK being one readout period.

Data d supplied to the register group aη of the data control unit 01. -dS is held for an appropriate period, for example, 4 clock cycles, as shown in FIG.
As shown in FIG. 8, four pieces of image data D2 . Ds.

D4 and D5 are each obtained continuously every one clock period T0. Thereafter, an image is displayed at normal density on a display unit (not shown) using image data that has been subjected to arithmetic processing in the same manner.

In the above-mentioned normal display mode, as is clear from FIG. 4K, six pieces of data d0 to d5 are read out in four clock cycles, and the access time of RAMs 61) to 61 is apparently shortened. .

Note that in the normal display mode, as described above, the fourth to sixth RAs connected to, for example, the second data bus)
M (b) ~ (b) are not used, but for example, CD-RO
The data on a certain screen of M is stored in the first to third RAMs (3υ~0
It is also possible to write the data of the next screen of the CD-ROM into the fourth to sixth RAMs (14 to 14) during the period when the data is being read from :), and read both of them alternately.

G4 Write operation in double density display mode Next, a write operation in double density display mode according to an embodiment of the present invention will be described with reference to FIGS. 5 and 6.

In the double density display mode, the distributor 9 is controlled by the distribution control signal ns from the address control section 0, and the first to
3rd RAM (31) to (to) and 4th to 6th R
Two sets of AM0 field ~ (g) are used simultaneously, and for example, 95. Data is transferred to the buffer memory in units of four times the period Te of the clock CLK having a repetition frequency of MHz.

A writing time chart in the double-density display mode is shown in FIGS. 5A-P, and A-E, G, and H in the same figure are the same as corresponding FIGS. 2A-E, G, and H, respectively.

On the other hand, FIG. 5F shows each address of the first to sixth RAMs (31) to 0, which are arranged in m rows and n columns throughout the first to sixth transfer cycles, and are arranged in m rows and n columns in the seventh transfer cycle PT7. and m lines (
n+1) columns.

In addition, the timings of FIG. 5 J, K, and L are different from those of FIG. 2 J, K, and L, respectively. Second and third write enable signals ■1. ■2 and 3. Furthermore, in Figure 5 M, N, and P, No. 4. Fifth and sixth write enable signals WE4, Vl/E5 and Iku6 are shown.

In this embodiment, when writing in the double-density display mode, the first to sixth
In the transfer cycle PTI to PT6, the buffer memory (
1 from each address in row 5, column j to row 1, column (j+5) of
The th to 6th data d0 to d5 are extracted.

Through the first to sixth transfer cycles, each RAM (41) to
The addresses (to) are arranged in m rows and n columns, as shown in FIG. 5F. In addition, as shown in J, K, and L of the same figure, the first. Third and fifth (odd numbered) transfer cycles PT
I, PT3 and PT5, 1st. Second and third write enable signals ■1. The 1st, 3rd, and 5th data dO* are supplied to the corresponding RAMs (3η, 0s, and G1, respectively), and the 1st, 3rd, and 5th data dO* d2 and d4 are supplied to the 1st, 2nd, and 3rd RAM ( 31).

0'4 and 01, row m and column n, respectively. Furthermore, as shown in M, N, and P of the same figure, the second.
Each of the fourth and sixth (even-numbered) transfer cycles PT2, P
At T4 and PT6, the 4th. The fifth and sixth write enable signals WF; 4, WE5 and 6 are respectively supplied to the corresponding RAM O, 0→ and (G), and the second, fourth and sixth data d, , d.

and d5 is the fourth. n is written to addresses in m rows and n columns of the fifth and sixth RAM Be m (c) and (b), respectively.

Also in the six transfer cycles starting from the seventh transfer cycle PT7, the odd-numbered data '4s dB and d are sent in the odd-numbered transfer cycle in the same manner as described above. are respectively written to the address of the m row (n+1) column of the 1st second and third RAM Hs O'4 and 0], and the even numbered data d, , d are written in the even numbered transfer period. , and dll
is the fourth. The data is written to the addresses in the m rows and (n+1) columns of the fifth and sixth RAMs 04*C'→ and (c), respectively.

Thereafter, in the same manner, a series of data is sequentially and cyclically written into the first to sixth RAMs ('+1) to OQ, as shown in FIG.

05 Read Operation in Double Density Display Mode Next, the read operation in double density display mode will be explained with reference to FIG.

As mentioned above, in double density display mode, each RAM
01) Since the writing state of data to ~OQ is different from the writing state in the normal display mode, the read timing is also different from that in the normal display mode shown in Fig. 4M, as shown in Fig. 7 M and L. The timing is different.

As shown in FIG. 7 BE, the row address strobe signal RAS is output from the address control unit 1υ at time 1- before the start of the first read cycle, and at time t0. when the read cycle starts. and this t.

At time t and t2, which are sequentially delayed by Tc/2 from the time,
1st. Second and third column address strobe signals CAS
I, CAR2 and CAR3 are output. Of the address strobe signals, RAS is commonly supplied to the RAM (3), and CASI is supplied to the first and fourth RAM (3).
CA32 is supplied to the second and fifth RAM (3'4 and (c)), CAR3 is supplied to the third and sixth RAM (33 and (b)). to snatch

Time t when these CA31 to CA83 are first supplied.

*t+a each RAuO at t2]) s 64:
When eJ'4, <(and 01#) are accessed, access to the address in row m and column n is started. As mentioned above, these addresses in these RAMs contain data d0. d, :d2.d, and d4.d are written.

Time points t, .
In tsVC, as shown in G, H, and J of the same figure, the first
#2nd. third output enable signal OEI,
OH2 and OH2 are each RAM (31) 1 (34: C
3. (b) and 01. (B) will be supplied to each of them. Then, as shown in K in the figure, time t. , 1.
, 12, the access time is increased from the first data bus 041Kg1 to the third RAM0, 0→, (
) to odd-numbered data d0. d2. d4 is sequentially and cyclically read out, and as shown in the figure, time t. , 1. , 1. 4th to 6th RAM (to the second data bus)
Even-numbered data d from (b), (b), and (g).

A, , and d5 are sequentially and cyclically read out. These data are stored in the register (l1m) of the data control unit C1l.
(Ilb)e(lie) and (12m), (12
b) and (12a), respectively.

In this way, six pieces of image data d corresponding to one set of four pixels
0 to d5 are read. Thereafter, a series of image data is sequentially and cyclically read out from RAM0◇ to (g), with two cycles of the clock signal CLK being one read cycle.

The data d0 to d5 supplied to the register groups αη and a of the data control unit 01 are held for an appropriate period, for example, two clock cycles, as shown in FIG. 7 M, N, and P. During the second readout cycle starting from time t4, four image data D2°D, D2, and D corresponding to a set of four pixels as shown in FIG. Continuously obtained every time. Thereafter, in the same manner, the image data that has been subjected to the arithmetic processing is displayed at double density on a display unit (not shown).

In the above-mentioned double density display mode, as is clear from FIG. 7 M and L, six pieces of data d0 are displayed in two clock cycles.
~d5 is read n, and the access time for the RAMs 01) to (b) is further shortened compared to the normal display mode.

Effects of the Invention As detailed above, according to the present invention, a series of data is cyclically written in a plurality of memories, and this data is cyclically written into a plurality of memories.
Since the memory is arranged to extend over M, a memory access device can be obtained that can retrieve a series of data at a relatively high speed compared to the memory access time.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a memory access device according to the present invention, and FIGS. 2 and 3 are time charts and blocks for explaining the read operation in the normal display mode of the embodiment. 4 is a time chart for explaining the read operation in the normal display mode of one embodiment, and FIGS. 5 and 6 are time charts for explaining the filling operation in the double density display mode of one embodiment. Time Chart and Block Diagram FIG. 7 is a time chart for explaining the read operation in the double density display mode of one embodiment. 0I is a data control unit, 61) to (to) are RAM, Qη is an address control unit, and @ is a CPU. -1-1゜ generation 1 person Ito Sadagupa, ) same
Hidemori Matsukuma...
.

Claims (1)

[Scope of Claims] A write control means and a read control means are provided for respectively controlling writing and reading of a plurality of memories, and the write control means sequentially and cyclically writes a series of data to the plurality of memories, and reads the data from the plurality of memories. A memory access device characterized in that the control means sequentially and cyclically reads out the series of data from the plurality of memories at predetermined intervals that are relatively fast with respect to the access time of the memories.