JPS5946681A - Pattern writing system for user's definition ram - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a writing method for writing arbitrary patterns, such as characters, desired by a user into a user-defined RAM.

As shown in Fig. 1, when the keyboard 1 of a small electronic computer (so-called personal computer) is operated, the
Characters such as letters and numbers are displayed on RT2. CR
In order to display characters, etc. on the screen of T2, it is necessary to constantly scan the CRT screen and refresh the screen. For this reason, data to be displayed is stored in the video RAM 3 (hereinafter referred to as V-RAM), and the screen is refreshed based on this content. V-RAM3 has CP
Data is written through U4, but since the written data uses ASCII code, it cannot be displayed as characters as is. A character ROM 5a (hereinafter referred to as C-ROM) converts a character code into a character pattern, creates a video signal via a control circuit 6, etc., and outputs it to the CRT 2. Currently, C-ROM5a
Assuming that the capacity is 2K bytes, this C-ROM5a
The upper 8 bits of the address are given from the V-RAM 3, and the lower 3 bits are given from the CRT controller 7 as raster addresses RA2 to RA0. The upper 8 bits specify the address of each character when displayed on the screen, and the lower 3 bits specify the address of a raster (one line) within one character (8×8 dot configuration).

General-purpose character patterns such as letters, numbers, and predetermined symbols are written in advance in the C-ROM 5a.
Only specific character patterns are output by addressing. On the other hand, in parallel with this C-ROM 5a, there is a user-defined RAM 5b (hereinafter referred to as character RA) for writing a unique character pattern defined by the user.
M and C-RAM) are prepared. In order for the user to display any character he or she has defined on the CRT2, the character pattern must be stored in the C-RAM in advance.
It must be written in 5b.

The present invention relates to this writing method.

As shown in FIG.
This C directly from the CPU 4 via the multiplexer 8 that switches between the PU 4 and the V-RAM 3.
- Address specification was made to RAM5b.

However, when the C-RAM 5b is accessed directly from the CPU 4, the I/O map of the CPU 4 (the I/O map normally uses the memory built into the CPU area)
The problem is that the memory capacity of the C-RAM 5b has to be distributed between the two, which complicates control and also complicates the address line switching circuit system.

Therefore, the present invention was made in view of the above problems, and when writing a pattern desired by a user to a user-defined RAM (C-RAM), it is possible to specify an address without directly specifying the address of the C-RAM by the CPU. The purpose of this invention is to improve the C-RAM addressing method.

That is, the present invention writes a pattern defined by a user into C-RAM via an unused area of V-RAM in which a character code is written.
The C-RAM address previously written in the unused area of M is outputted from the V-RAM at predetermined intervals, and the pattern data sent from the CPU is raster-sequentially transferred to the C-RAM.
Its basic feature is that it can be written in.

Examples will be explained below.

First, the V-RAM 3 (FIG. 1), which forms the background of the idea of this invention, will be explained with reference to FIG. 2.

FIG. 2 shows the relationship between the number of characters displayed on the screen and the memory address of the V-RAM 3. V-RAM3 has a capacity of 2K bytes (numbers 0 to 2047) and is compatible with CRT
The number of characters displayed on 2 is 2000 (80 columns x 25 lines). The address used to display the screen is 0 to 19.
99, and the area from address 2000 to address 2047 is an unused area that is not involved in display at all. And V-RA
Addressing of M3 is performed from the CRT controller 7 via the multiplexer 9 in the order shown in FIG.

Therefore, C-RAM is installed in these addresses 2000 to 2047 in advance.
By writing the address of 5b, there is no need for the CPU 4 to directly specify the address.

A circuit configuration based on this idea is shown in FIG. As can be seen by comparing the circuit in Figure 1, multiplexer 8 and CPU
Address bus 10b from 4 to multiplexer 8 is omitted.

User-defined character pattern (8x8 dots)
To write the character pattern into the C-RAM 5b, the user first determines the code of the character pattern.

Next, the CPU 4 specifies addresses 2000 to 2047 of the V-RAM 3 via the address bus 10a and the multiplexer 9, and the data bus 11 is also specified from the CPU 4.
, the code data is sent as write data via the bus buffer 12.

User-defined character codes, ie, addresses of C-RAM 5b, are written in all addresses 2000 to 2047 of V-RAM 3.

The CRT controller 7 operates regularly based on a counter and the like in order to display characters and the like on the CRT 2. This CRT controller 7 has an address bus 10c,
A 12-bit address MA0 to MA11 is applied to the V-RAM 3 via a multiplexer 9.

Addresses MA0 to MA11 change regularly as shown in FIG.

Now, when the screen enters the vertical retrace engine, the CRT controller 7 addresses address 2000 of the V-RAM 3. 1
Addresses 2000 to 2047 are addressed in the first period of H (one horizontal scanning period). Since one dot clock of screen display is about 69 ns and one character is 8×8 dots, the time to scan addresses 2000 to 2047 is about 26.5 μs (69 ns×8×48). A timing chart is shown in FIG.

The V-DISP signal is based on a vertical synchronization signal and indicates that the vertical retrace period has begun. When this V-DISP signal is detected by the CPU 4, the CPU 4
5b on-chip enable CE is set to “LOW” for a predetermined period.
Make it. Only data can be written to the C-RAM 5b.

On the other hand, in synchronization with the falling edge of the V-DISP symbol, C-
Raster addresses RA0 to RA2 giving the lower three bits of the address of RAM 5b are input to C-RAM 5b.

The first 1H (of which 26.5
within μs), and the same address data (C-
raster 0 of the character pattern with the upper 8 bits of the address of RAM 5b) and the raster address "000"
(8 dots = 8 bits = 1 byte) is C-RAM5b
will be written to. 1 byte data of raster 0 is CP
C from U4 via data bus 11 and bus buffer 13
- Sent in synchronization with RAM/CE signal.

The first CE signal is created based on the V-DISP signal becoming "LOW". The following seven CE signals are generated at an interval of 63 μs, that is, one horizontal scanning period from the first CE signal. This can be created by software processing, for example, by combining small instructions and adjusting the timing so that the processing time is 63 μs. In the second H after entering the vertical retrace period, 2000 of V-RAM3
Addresses .about.2047 are scanned again, and the same data, that is, the same character address of the C-RAM 5b as before, is output, and since the raster address is "001", raster 1 of the character pattern is written. Of course, this character pattern data (1
byte) is sent from the CPU 4 in synchronization with the second CE signal.

For the subsequent 3rd H, 4th H, etc., raster 2 and raster 3 are written in exactly the same way, respectively.
Raster 7 at the 8th H (raster address "111")
When written, the character pattern (8x8) C-
Writing to RAM 5b is completed.

Note that the raster data to be sent from the CPU 4 in synchronization with the CE signal may be assembled in advance as a program and sent from the input section of the keyboard 1 according to the execution of the program, or alternatively, it may be input by directly operating the keyboard 1. It may be created as data. In any case, C-R at a predetermined timing based on the judgment of the CPU 4.
AM5b.

In addition, in the above embodiment, V-R, which is not related to screen display,
All addresses 2000 to 2047 of AM3 were used,
There is no particular need to use all of them; 1/2 or 1/4 of 48 addresses may be used. The same thing can be accomplished with at least one address (although additional controls such as latches are usually required). However, it is preferable to use all addresses as in the embodiment, since this provides a margin of timing. Although the CRT controller 7 only shows the address scan function in FIG. 3, like known CRT controllers, in addition to generating scan addresses and raster addresses, it also generates signals such as H sync and V sync that are the basis of screen display. It also creates the following. Also, C connected in parallel
-Switching between ROM5a and C-RAM5b is done by V-RAM
3 is doing it himself.

As described above, this invention utilizes the memory area of the video RAM that is not involved in screen display without specifying the address of the character RAM by the CPU.
There is no need to allocate the memory capacity of the character RAM on the I/O map of the CPU, so the memory in the CPU area can be used for other functions, and the multiplexer that switches between the CPU and video RAM can be omitted, simplifying the address circuit. effect is achieved.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram based on the conventional method, Fig. 2 is an explanatory diagram of the relationship between the number of characters displayed on the screen and the memory address of V-RAM, and Fig. 3 is a circuit diagram based on the method of the embodiment. , FIG. 4 is a diagram showing the write timing of C-RAM. 2...CRT, 3...Video RAM, 4...CP
U, 5b...Character R as user-defined RAM
A.M.

Claims (3)

[Claims] (1) A method of writing an arbitrary pattern desired by the user into the user-defined RAM, in which an address of the user-defined RAM is generated from an unused area of the video RAM in which the character code is written, and the pattern is written into the user-defined RAM. A pattern writing method to a user-defined RAM is characterized in that the pattern is written to a user-defined RAM. (2) Write the address of the user-defined RAM into an unused area of the video RAM via the CPU, and then
A method for writing a pattern into a user-defined RAM according to claim 1, wherein data for each raster of the pattern is sequentially sent from a CPU. (3) The unused area of the video RAM is a user-defined area according to claim (1) or (2), wherein the unused area is a storage area at at least one address corresponding to a vertical blanking period of a video signal. Pattern writing method to RAM.