JP2506959B2 - Display data processing device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display data processing device for displaying on a display device using a microcomputer.

2. Description of the Related Art In recent years, efforts have been made to improve the functions and performances of various electronic devices, and a display data processing device using a microcomputer that is involved in drive control of these electronic devices is also required to have high functions.

In a data processing device related to CRT display such as a TV receiver, processing is performed including data for displaying channels, volume, etc. on the screen. Fig. 4 shows a CR that outputs characters to the cathode ray tube (CRT).
The block diagram of T indicator is shown. Character display signal VOW and video signal VO
UT and UT are combined, the combined signal is input to the CRT, and a character is displayed on the screen by selectively applying a drive voltage to the character display signal VOW in synchronization with the scanning of the CRT.

Figure 2 directly drives such a CRT display,
It is a block diagram of a conventional display data processing device formed using a one-chip microcomputer.

In FIG. 2, 1 is a CRT display, 2 is a one-chip microcomputer, 3 is a central processing unit (hereinafter CPU).
4) ROM storing execution instructions of CPU3, 5 CPU
3 is a general-purpose RAM that reads and writes data required in the process of executing various commands in response to commands from ROM 4, 6 is a display-only RA that stores character data for display that drives the CRT display 1.
M and 7 are C according to the display character data from the display-only RAM6
It is a CRT control unit 7 that drives the RT display 1.

FIG. 3 is a block diagram showing a specific configuration of the display-only RAM 6 and the CRT control section 7 shown in FIG. In FIG. 3, 3 is a CPU, 6 is a display-only RAM, and 8 is a display-only RA.
A character generator that converts the display character data from M6 into character shape data, 9 shifts the character shape data, and corresponds to each of the character shape divisions A to G shown in FIG. 5, for example. A shift register for generating a character display signal as shown in a to g of FIG. 6, a display control circuit 10 for generating timing by a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC and a CRT display oscillation signal DOSC, 11 is a data Bus 12 is an address bus. These buses 11 and 12 are connected to the CPU 3. The character generator 8, shift register 9 and display control circuit
10 constitutes the CRT control unit 7 shown in FIG.

In the above configuration, the writing of the display character data is performed as follows. First, the CPU 3 specifies the addresses A _{00 to} A _5F corresponding to the display character positions to the display-only RAM 6 as shown in FIG. 7, and then the character data at each display character position is transferred from the CPU 3 to the display-only RAM 6, These character data are respectively written in the corresponding addresses of the display-only RAM 6.

On the other hand, the reading of the display character data is performed as follows. The vertical sync signal VSYNCC, the horizontal sync signal HSYNC, and the CRT display oscillation signal DOSC are input to the display control circuit 10, and when the scanning of the CRT comes to the display character position, the address display dedicated RAM 6 corresponding to the display character position is displayed. It is added as an address signal to access the display-only RAM6. As a result, the display character data D _{00 to} D _5F stored in the respective addresses A _{00 to} A _5F of the display-only RAM 6 are sequentially read out and input to the character generator 8.

The display character data input to the character generator 8 is converted into character shape data corresponding to, for example, the portions A to G shown in FIG. 5 by a control signal from the display control circuit 10 and added to the shift resist 9.

In the shift register 9, by the control signal of the display control circuit 10, character display signals a to g shown in FIG. 6 corresponding to the character shape data A to G shown in FIG. Apply to the CRT display 1 synchronously, and CR
T Display a character at a predetermined position on the screen.

Problems to be Solved by the Invention Improvement in functionality of many electronic devices such as TV receivers,
As the performance becomes higher, the microcomputers that control them are required to have higher functions. The higher the function of the microcomputer, the larger the size of the ROM that stores the program, and thus the size of the microcomputer itself.

Under such circumstances, in the case where the dedicated RAM 6 needs to be provided separately from the general-purpose RAM 5 like the conventional data processing device, the increase in chip size cannot be avoided, which is extremely inconvenient. Moreover, as is clear from the above description of the conventional example, since the display-dedicated RAM 6 is accessed by both the CPU 3 and the display control circuit 10, it is necessary to configure it as a so-called dual-port RAM having two lines of address lines. Therefore, the chip area is increased more than the addition of the usual single port RAM. Also, since the display-only RAM 6 has a dual-port configuration, this function cannot be simply applied to the general-purpose RAM 5 having a single-port configuration.

It is an object of the present invention to provide a display data processing device that solves such a conventional problem.

Means for Solving the Problems A data processing device of the present invention includes a CPU having a microinstruction memory, a ROM storing execution instructions of the CPU, character data for CRT display at a predetermined address, and normal instruction execution. General-purpose RAM to store the data used for, and direct memory access (DMA:
Direct Memory Access) Generates a request signal
Read the display character data stored in the general-purpose RAM by accessing the general-purpose RAM by using the DMA request signal generator that separates the RAM from the control of the CPU and the drive signal from the signal generation circuit as an address signal, A display data save buffer that stores the read display character data, a character generator that converts the display character data into character shape data, and a character display signal that corresponds to the character shape data in synchronization with the CRT scan. And a display control circuit for controlling the display data saving buffer, the character generator and the shift register.

According to the display data processing device of the present invention, the DMA request signal is used as a kind of interrupt request signal, and when the general-purpose RAM is removed from the control of the CPU at the time of character display of the CRT, the drive signal output from the signal generation circuit is generated. The general-purpose RAM can be accessed as an address signal instead of the address from the CPU. For this reason, a CRT is used as part of the single-port general-purpose RAM.
It becomes possible to store the display data, and access it when displaying characters to read the display character data. This eliminates the need for dual port dedicated RAM.

Embodiment An embodiment of the display data processing device of the present invention will be described with reference to the block diagram shown in FIG. FIG. 1 shows a CPU and a general-purpose of a CRT display data processing device according to an embodiment of the present invention.
It is a block diagram showing a RAM and a CRT control unit.

In FIG. 1, the same parts as those in the conventional example shown in FIGS. 2 and 3 are designated by the same reference numerals. The microcomputer 2 includes a DMA request signal generator 13 and a C instruction circuit 14 which decodes the request signal and gives a read instruction to the general-purpose RAM 51.
PU31, single-port general-purpose RAM 51 for storing character data for CRT display at a predetermined address, display data save buffer 15 for storing one line of display character data in dual port configuration during the display A character generator 8 for converting display character data into character shape data, a shift register 9 for generating a character display signal corresponding to the character shape data, and applying this signal to the CRT display in synchronization with the scanning of the CRT, A display data save buffer 15, a display control circuit 10 for controlling the character generator 8 and the shift register 9 are provided. The character data for display is not the conventional display-only RAM6, but the general-purpose RAM51.
It is written in the predetermined addresses A _{00 to} A _5F in the.

In the above configuration, the display character data is written to the general-purpose RAM 51 by writing the display character data transferred from the CPU 31 via the data bus 11 to the address designated by the CRU 31 via the address bus 12. . Note that the remaining addresses of the general-purpose RAM 51 store data that is used during the execution of normal instructions other than CRT display driving.

Next, when displaying characters on the CRT, a DMA request signal is input to the μROM 14 in the CPU 31 from the DMA request signal generator 13 in the CRT controller as a kind of interrupt request signal. μROM14 is usually C
It is used for instruction decoding of PU31. When it receives a DMA request signal, it gives a read instruction to general-purpose RAM51 and at the same time disconnects this general-purpose RAM51 from under the control of CPU31. Therefore, thereafter, an address signal corresponding to the display character position obtained from the display control circuit 10 is added to the general-purpose RAM 51 via the address bus 12, and the general-purpose RAM 51 is accessed. As a result, the display character data stored in the addresses A _{00 to} A _5F of the general-purpose RAM 51 are sequentially read out via the data bus 11. The read display character data is sequentially displayed in the display data save buffer in synchronization with the read command from the μROM14.
It is transferred to 15, and is held at the address corresponding to the middle column.

The display character data held in the display data saving buffer 15 is sequentially read out to the character generator 8 by the address signal corresponding to the column of the display character position added from the display control circuit 10. The display character data read by the character generator 8 is converted into character shape data and input to the shift register 9, and the display control circuit 10
A character display signal is applied to the CRT display 1 in synchronism with the scanning of the CRT by a control signal from, and a character is displayed at a predetermined position on the CRT screen.

Note that when such a DMA method is used, normal instruction execution is temporarily suspended, but actually 10 to every 10 msec.
It only interrupts for about μsec, and the execution speed only decreases by about a few percent. Therefore, there is almost no problem in programming.

According to the display data processing device of the present invention, the display data of the CRT is stored at a predetermined address of the general-purpose RAM in the microcomputer, and the DMA request signal is generated at the time of the character display of the CRT to generate the general-purpose data. The RAM is separated from under the control of the CPU, and then the display character position from the display control circuit is used as an address signal to access the above-mentioned general-purpose RAM to read the display character data in the general-purpose RAM. Since it is designed to drive the CRT display by transferring it to the generator and shift register, it is not necessary to provide the dedicated dual-port RAM shown in the conventional example with only general-purpose RAM, and therefore the chip size of the microcomputer. Can be made smaller. Moreover, since various CRT displays can be driven simply by enlarging or reducing the display character data area of the general-purpose RAM, the versatility of the data processing device is enhanced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a display data processing device of the present invention, FIG. 2 is a block diagram of a conventional data processing device for CRT display, and FIG. 3 is a block diagram showing a main part of FIG. FIG. 4 is a diagram of a display device to be driven in the present invention and a conventional example, FIG. 5 is a concrete display character shape diagram, FIG. 6 is a waveform diagram of a character display signal, and FIG. 7 is a display character position. It is the figure which showed and its address. 1 ... CRT display, 2 ... microcomputer, 31 ...
... Central processing unit (CPU), 4 ... ROM, 51 ... General-purpose RA
M, 8 ... Character generator, 9 ... Shift register, 10 ... Display control circuit, 11 ... Data bus, 12 ...
Address bus, 13 ... DMA request signal generator, 14 ... μRO
M, 15 ... Display data save buffer.

Claims (1)

(57) [Claims] 1. A central processing unit having a micro instruction memory, and a ROM storing execution instructions of the central processing unit.
Under the control of the central processing unit, a single-port general-purpose RAM that stores display data of the display device and data used for normal instruction execution at a predetermined address, and a DMA when displaying the display data on the display device. A DMA request signal generator that generates a request signal and controls the data of the single-port general-purpose RAM independently of the control of the central processing unit, and the single port using the signal from the DMA request signal generation circuit as an address signal. A display data save buffer for storing the display data stored in the single-port general-purpose RAM by accessing the general-purpose RAM,
A display data processing device, comprising: a display control circuit that controls the display data saving buffer to display the display data on a display device.