JPS60164796A - Image display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in an image display device capable of displaying character patterns on a display.

Conventionally, as an image display device of this kind, there is a system in which the size of displayed characters on a CRT display is changed by changing the frequency of the dot clock fa to change the display time per dot constituting the character. With this method, the character size can be changed on a screen-by-screen basis, but in order to display characters with different sizes on the same screen, it is necessary to
The configuration of the T display interface, especially the timing generation circuit, becomes complicated and is difficult to implement.

The present invention has been developed in view of these circumstances.
An object of the present invention is to provide an image display device with excellent visibility of display information and a large visual effect by displaying character patterns of different character sizes in a composite manner on the same screen of a display.

Hereinafter, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of an embodiment of the image display device of the present invention, in which 1 is a central processing unit (hereinafter referred to as CPU), 2 is a system consisting of an address bus, a data bus, and a control path. path, 3 is read-only memory (
4 is a read/write memory (hereinafter referred to as RAM), 5 is a CRT display interface, 6 is a CRT display, 7 is an interface, and 8 is an external device.

In this configuration, CPU 1 CR converts the letter j turn according to the program registered in ROM 3.
The image is displayed on a CRT display 6 via a T display interface 5.

The CRT display interface 5 includes an interface control circuit 11, an oscillator 12, a multiplexer 13, a timing generation circuit 14, and an address buffer 15.
, screen control data register 16, multiplexer 17,
Image memory 18, image data read register 19, image data write register 20, character code register 21,
Attribute data register 22, letter and turn generator 23, parallel/serial conversion circuit 24, image signal synthesis circuit 25
It consists of

” 1. The image memory 18 has a capacity for multiple double-sided images, and
The screen to be displayed can be switched using control data from the PU 19. Various methods can be considered for writing or reading image data into the image memory 18, but here we will use the image memory 18 in the address space of the CPU 1. Assigned within
It is assumed that data is read and written directly from the CPU1.

Next, the operation of the CRT display interface (hereinafter referred to as "interface") 5 will be briefly explained. That is, the image memory 18 in the interface 5
is accessed from CPU1 (CPU mode), or
It can be accessed (display mode) from the timing generation circuit 14, and the timing generation circuit 14 selects the mode so that there is no conflict between the two modes. When in CPU mode, address information Acp is sent from system path 2 via element 11.
is loaded into the address buffer 15, the address line of the image memory 18 is set via the multiplexer 17, and the image data (character code and attribute data) given and received between. On the other hand, in the display mode, the address information Ad for accessing the image memory 18 is based on the in-screen address information Ada output from the timing generation circuit 14 and the screen selection information Adn set in the data register 16.
s is combined, the address line of the image memory 18 is set via the multiplexer 17, and the character code D is set. h is stored in the character code register 21 as attribute data Da such as color code cursor generation 1 character mother turn inversion 1 etc.
t is loaded into data register 22. Under the control of the timing generation circuit 14, character patterns D and t are generated from the character code Dch loaded into the character code register 21 by the character number and turn generator 23, and are converted to the parallel-to-serial conversion circuit 24. , and is sent to the image signal synthesis circuit 25 as serial data Dllr. On the other hand, the attribute data Dat loaded into the data register 22 is sent to the image signal synthesis circuit 25, and the timing generation circuit 1
4, a screen control signal Cay such as a horizontal synchronization signal and a vertical synchronization signal 2 is sent to the image signal synthesis circuit 25, and the data D
The image signal Dds is generated by combining ir+5-D&t and the signal Csy, and is sent to the CRT display 6. This is J,
A character pattern is displayed on the CRT display 6.

Here, the timing generation circuit 14 selectively inputs the dot clock fa1'J or fa2 outputted from the oscillator 12 via the multiplexer 13, and determines the number of display dots per character stroke, the number of display characters per line, and the number of display characters per line per screen. Cch+Cyg+CrB+CBhv Signals that count the number of displayed lines, etc., and control the two screens of elements in the interface, such as the space between two lines between characters, horizontal and vertical synchronization signals, etc.
Generate CBy. dot clock fd1. fd2
is switched by the character size data S1 set in the control data register 16.

The screen control data register 16 allows switching of display screens and character sizes. Figure 3 shows the port address of the screen control data register 16, and J and 5IZE are the display character size setting flags (Sl).
, 1 is a 6-double size character, and O is a regular size character. PICT indicates screen selection information (Adn), and is PICT 2 in the illustrated example.

This means that 8 screens from screen numbers 0 to 7 can be switched by the 3-bit no/turn of 1.0.

The operation of one embodiment of the image display device according to the present invention will be described below with reference to FIGS. 4 and 5.
The figure is a flowchart for initializing the display screen switching logic. In the figure, PICTNO is the screen number, np is the maximum screen number to be switched and displayed, nd is the number of screens to be switched and displayed, and j is the display screen switching counter. be.

FIG. 5 is a flowchart when switching the display screen, and in the figure, CNDATA is the screen control data (D
en), CTRLi indicates character size control data for screen number l.

Display data 0 is written in the screen number O of the image memory 18 as shown in al in FIG. 6, and display data 1 is written in the screen number 1 as shown in bl in FIG. 6 in advance by a display data writing routine (not shown). It shall be kept in mind. In alebl in FIG. 6, a blank space indicates that a blank character code that is not displayed on the CRT display 6 is written. In the case of FIG. 6, the constants in FIGS. 4 and 5 are n, =01H+nd=02. So, the character size control data CTRL 1 is CTRL O=80H.

CTRL 1 = 00H. The subscript H means hexadecimal representation.

The display screen switching logic is initialized according to the processing flow shown in FIG. 3, and the processing flow shown in FIG.
The structure is such that the screens to be displayed are sequentially switched. In the process flow shown in FIG. 4, in process 101, the system is initialized, that is, the work area is initialized, input/output devices are initialized, etc., and then in process 102, the screen number P I CTNO is changed to the maximum value of the screen number to be displayed. n, and a counter j is initialized to the number nd of screens to be switched and displayed, and the process moves to other processing logic of process 103.

The processing flow shown in FIG. 5 will be explained. After the contents of the register are saved in the stack area in process 201, the screen number PICTNQ is set in l in process 202.

In process 203, character size control data CTRLi is read out, an OR operation is performed with the screen number plcTNo, and screen control data CNDATA is obtained. In process 204, process 20
Port the result screen control data CNDATA obtained in step 3)
(CNPICT), and the display screen is switched to the screen indicated by the screen number PICTNO and displayed in the specified character size. In processes 205 to 209, preparations for the next process are made. In process 205, the screen number PIC
Decrease TNO by 1. Process 206 decrements the value of counter j by one. The judgment logic 202 judges whether or not j is NO. When j is NO, the process moves to process 210, and when j=o, the process moves to process 210 after executing processes 208 and 209. Processing 20
8 is the maximum value n of the screen number for switching and displaying the screen number P I CTNO.

, and a process 209 resets the value of the counter j to the number nd of screens to be switched and displayed. In process 210, processes other than display screen switching logic are performed, and in process 211, the contents of the register are restored from the stack area, and the process ends.

9- In the case of the example in Figure 6, display data 0 (shown at) written to screen number O and display data 1 (shown b) written to screen number 1 alternate at a constant cycle. The results displayed,
To the human eye, it appears as shown in cl due to an afterimage effect. 7th
The illustrated example is also similar to FIG. 6.

When the display screen is switched at a constant cycle using the process flow illustrated in FIGS. 4 and 5 via the screen control data register 16 having the port address illustrated in FIG. 3,
To the human eye, only the display data portion of each screen is reflected as an afterimage, making it appear as if it were a single screen.

Note that the timing for switching the display screen shall be appropriately determined within a range that is not shorter than the period of the vertical synchronization signal.

When the dimensions of the displayed characters are controlled from the screen control data register 16 as in the example circuit, it is possible to improve visibility by combining a screen created with fixed-sized characters and a screen created with double-sized characters. In addition, it is possible to display displays with great visual effects.

According to the present invention described above, in an image display device that has an image memory for multiple sides and can display data stored in the image memory on a display, display positions on the screen of the displays overlap each other. means for dividing and writing data to be displayed in a composite manner on multiple screens onto different screens; Since it is equipped with a switching means to make it almost the same as the synchronization signal, it can be made to look like a single screen by using the human afterimage effect, and it is necessary to consider how to combine the screens to be synthesized. This makes it possible to provide an image display device with excellent visibility and great visual effects.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of an image display device according to the present invention, FIG. 2 is a block diagram showing a specific example of a CRT display interface of the same embodiment, and FIG. 3 is a screen of FIG. 2. 11- Construction circuit. FIGS. 4 and 5 are flowcharts showing the state address of the control data register, and FIGS. The diagram is C
FIG. 6 is a diagram for explaining different character patterns (data) displayed on the RT display. 1... Central processing unit, 2... System path, 3
. . . read-only memory, 4. read/write memory, 5. CRT display interface, 6.
...CRT display, 7...interface,
8... External device, 11... Interface control circuit, 12... Oscillator, 1.9, 17... Multiplexer, 14... Timing generation circuit, 15... Address buffer, 16... screen control data register,
18... Image memory, 19... Image data read register, 20... Image data write register, 2.
...Character code register, 22...Attribute data register, 23...Character pattern generator, 24.
...Parallel-serial conversion circuit, 25...Image signal board 12- Applicant's sub-agent Patent attorney Takehiko Suzue 13- Fig. 1 Fig. 3 Fig. 5 s6 Fig. 7

Claims (1)

[Claims] In an image display device that has image memory for multiple sides and can display data stored in this image memory on a display, the data is synthesized on multiple screens so that the display positions on the screens of the displays do not overlap with each other. A means for dividing and writing data to be displayed on different screens, and a switching means for switching the screens written by this means at a constant cycle, and making the switching cycle almost the same as the vertical synchronization signal of the display. An image display device comprising: