JP2891429B2 - Liquid crystal display controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Table of Contents] Overview Industrial application field Conventional technology (Fig. 4) Problems to be solved by the invention Means for solving the problem (Fig. 1) Action Embodiment (Fig. 2) , FIG. 3) Effects of the Invention [Overview] Regarding the liquid crystal display control device, even if the display dot size of the main body of a personal computer or the like and the display dot size of the liquid crystal display are not the same, if the liquid crystal side has a larger size. A display data memory unit; and a memory control unit, wherein the display data of the main unit can be displayed on the liquid crystal.
A liquid crystal display control device for displaying, on a liquid crystal display, data written in said display data memory means by said memory control means, comprising: address output means for outputting an address corresponding to a displayable area of the liquid crystal display; The address data in the x direction and the y direction output from the display data memory means are respectively converted into addresses in the x direction and the y direction corresponding to the memory area of the display data memory means, and mask control means. When transferring the held data to the liquid crystal display means, the display data memory means is read by the output signal of the address conversion means, and the area not transferred to the liquid crystal display means is controlled by the mask control means so as not to write data.

[Industrial applications]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display control device, and more particularly to a device for displaying data of a data processing device main body even on a liquid crystal display having a size larger than a display memory size of the data processing device main body.

[Conventional technology]

2. Description of the Related Art In recent years, in data processing devices such as personal computers and workstations, liquid crystal displays have been required as display devices for saving space and energy.

In a conventional liquid crystal display control circuit for a data processing device, as shown in FIG. 4A, the number of dots that can be displayed on a liquid crystal display device (hereinafter referred to as an LCD device) and the number of dots that can be displayed on the main device of the data processing device. (For example, 1024 × 768 dots). A memory is configured according to the number of display dots, and the memory data is transferred to the LCD device on a one-to-one basis.

In addition, in the LCD device, the screen is divided into upper and lower parts to constitute one screen. Therefore, when writing data to the display memory 60 of the main unit, as shown in FIG. 4A, data is sequentially written from the first part of the address of the display memory 60, but after writing for one frame, When this is written to the LCD unit 70, the LCD unit 70 actually writes the data to the upper LCD unit and the lower LCD unit at the same time.
In, the upper part is read from the RA position, and the lower part is read from the RB position. Then, the data read from the upper and lower portions are simultaneously written in the upper LCD portion and the lower LCD portion of the LCD portion 70.

FIG. 4B schematically illustrates the configuration. The display memory 60 is composed of two memories, a first half memory 60-1 and a second half memory 60-2.

When writing data in the display memory 60, the memory control unit 61 outputs a write enable signal to the first half memory 60-1, and the address control unit 62 outputs an address. After the data is written in the first half memory 60-1, the memory control unit 61 outputs a write enable signal to the second half memory 60-2, and the address control unit 62
It outputs the same address as 60-1. In this way, data is sequentially written in the first half memory 60-1 and the second half memory 60-2.

When reading data from the display memory 60 and writing the data in the LCD unit 70 of the liquid crystal display device 64, the memory control unit 61 does not output the write enable signal WE, but outputs the output enable E and outputs the address control unit 62. The address is transmitted to the memory 60.

As a result, data is simultaneously sent to the LCD unit 70 from the first half memory 60-1 and the second half memory 60-2.

The LCD unit 70 has the first half memory 60-1 and the second half memory 60-
2 has a data shift register for receiving the data transmitted from the second and the third data shift registers. These data shift registers are transferred in 8-bit units. That is, according to the address from the address control unit 62, each 8 bits
The data is transferred to each data shift register of the D section 70. LCD controller 63 at this time, in synchronization with the read control of the address control unit 62, and outputs the data shift register clock XSCL, the data line latch clock YSCL, the scanning start signal D _iN the LCD unit 70. The XSCL sequentially shifts input data to a shift register in one horizontal scanning direction of the display, that is, an X direction. When one line of data is input, the YSCL is output, the one line of data is latched, and the next one line of data is input again by XSCL and shifted. Thus, data for one frame is input. Note that the _DiN is input at the beginning of inputting data for one frame.

The data read from the display memory 60 in this manner is sequentially held and displayed on the LCD unit 70.

[Problems to be solved by the invention]

In conventional liquid crystal display control, the number of dots that can be displayed on the liquid crystal display device matches the number of dots displayed in the display memory of the main unit, that is, the memory size matches. A memory for data transfer, and memory data is transferred on a one-to-one basis from the display memory of the main unit to the LCD unit of the liquid crystal display device.

However, the number of display screen dots (display screen size) varies depending on the type of main unit such as a personal computer, and in the past, the LCD unit was selected in accordance with the number of front surface display dots of the main unit.

As described above, since the display size of the liquid crystal display device is selected in accordance with the main device, if the number of display dots of the main device is different, the type of the liquid crystal display device increases accordingly, resulting in a problem that the cost increases. .

Accordingly, an object of the present invention is to provide a liquid crystal display control system in which the same liquid crystal display device can be used for a display memory of a main unit having the same or smaller size in order to solve such problems. It is to provide.

[Means for solving the problem]

In order to achieve the above object, in the present invention, FIG.
As shown in the figure, the display memory of the main unit is 1 and the LCD unit is 1
When the value is set to 0, the size of the LCD unit 10 is set to be larger than or equal to the size of the display memory 1, and the display data of the display memory 1 is displayed in the LCD unit 10 as indicated by 1 '.

Therefore, as shown in FIG. 1 (B), when data D is written in the display memory 1 of the main unit, the address of the display memory 1 is output from the memory control unit 2 and the address is passed through the multiplexer 5. Is transmitted to the display memory 1 and the data D is written. At this time, the write enable signal WE from the memory control unit 2 is first output to the upper half memory 1-1 to be written, and then the lower half memory 1
-2. Thus, at the time of writing, the same address is output twice from the memory control unit 2 to the display memory 1.

By the way, in order to display on a liquid crystal display device,
It is necessary to transfer the data of the display memory 1 to the LCD unit 10. In this case, since the size of the LCD unit 10 is larger than the size of the display memory 1, the hatched portion 1 'in FIG. It is necessary to display the data other than the part other than zero. Therefore, a mask section 7 is prepared.

When the display data is transferred from the display memory 1 to the LCD unit 10, an address corresponding to the size of the large LCD unit 10 is output from the address control unit 3. Now, FIG. 1 (A)
, And outputs addresses sequentially from A. And when the address A ₁ point of the LCD unit 10, address translation as the start address of the display memory 1 from the address conversion section 4 is output. Ie line position
When counting the Y _1, Y _'0 of the starting address of the display memory 1 is instructed, the display memory 1 when the column signal is X ₁
Column signal is converted to indicate X _'0 of the head position. Then, after the X ₃ of the LCD unit 10 column signal has counted to clear the X direction address, increments the Y direction address. This allows the data in display memory 1 to be
It can be transcribed to a predetermined position in the D section 10.

In this case, in the LCD unit 10, a mask control unit 6 and a mask unit 7 are provided to prevent unnecessary data from being written in a portion of the display memory 1 where data is not written, and masks 7-1 and 7-2 are provided. The parts 10-1 and 10- of the LCD section 10
When 2 is addressed, mask off masks 7-1 and 7-2 and write zero. In FIG. 1B, the dotted line portion 10 'outside the display memory 1 is
Are shown in a pseudo manner.

[Action]

In this way, even if an LCD unit having a size different from that of the display memory is used, data of the display memory can be displayed at a predetermined position of the LCD unit.

〔Example〕

An embodiment of the present invention will be described with reference to FIGS.

FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram showing a state in which data of a display memory is displayed on an LCD unit.

2, the same symbols as those in FIG. 1 indicate the same parts, 1 is a display memory, 2 is a memory control unit, 3 is an address control unit, 4 is an address conversion unit, 5 is a multiplexer, 6
Is a mask control unit, 7 is a mask unit, 8 is a liquid crystal display control unit, 10 is an LCD unit, 11 is a CRT control unit, 12 is a synchronization circuit, 13
Is a video shift register, 14 is a data latch, 15 is a mode setting unit, 16 is an upper data latch, and 17 is a lower data latch.

The display memory 1 includes a first half memory 1-1 and a second half memory 1-2.
The first half memory 1-1 and the second half memory 1-2
Are accessed at the same address. When data is written, the write enable signal WE is selectively output to one of them, whereby the first half memory 1-1 and the second half memory 1-2 are selectively written. When reading data, the same address is given. Data is simultaneously output from the first half memory 1-1 and the second half memory 1-2.

The memory control unit 2 includes a read / write control unit 2-1 and an address output unit 2-2. Read / write control unit 2
-1 selectively outputs a write enable signal WE to one of the first half memory 1-1 and the second half memory 1-2 when writing data to the display memory 1. The address output section 2-2 includes a column direction address counter 2-3 and a line direction address counter 2-4, and each address signal output from these is transmitted to the display memory 1 via the multiplexer 5.

The address control unit 3 outputs an address signal when data is read from the display memory 1 and is transcribed to the LCD unit 10, and an X signal for outputting a column direction address is provided.
A direction counter 3-1 and a Y direction counter 3-2 for outputting a line direction address are provided. The address output from the address control section 3 is for pseudo-addressing the LCD section 10. That is, as shown in FIG. 3, 0 to Xn is output as the column direction address and 0 to Ym is output as the line direction address.

The address conversion unit 4 converts the address signal output from the address control unit 3 so as to control the data in the display memory 1 shown in FIG. 3 to be displayed on the inclined area 1 'of the LCD unit 10. And an X-direction converter 4-1 and a Y-direction converter 4-2. When X direction changing unit 4-1 to the X-direction counter 3-1 has counted X _1, counts up from 0, Y direction changing unit 4-2 Y direction counter 3-2
There operates counting up from 0 when the counted Y _1. The output addresses of these address converters 4 are
Since the signals are transmitted to the first half memory 1-1 and the second half memory 1-2 of the display memory 1 via the multiplexer 5, the X-direction counter 3-1 and the Y-direction counter 3-
2 is made read data from the display memory 1 when the instruction to A ₁ point of the LCD unit 10, so that this, as will be described later are displayed in the hatched region 1 '.

The multiplexer 5 selectively outputs an address signal transmitted from the address output unit 2-2 or the address conversion unit 4, and transmits the address signal from the address output unit 2-2 in a write mode for writing data to the display memory 1. Is output, and data is read from the display memory 1 and LC
Address conversion unit 4 in read mode to transfer to D unit 10
Output what is transmitted from

The mask control unit 6 does not display noise in a portion other than the hatched area 1 'of the LCD unit 10 shown in FIG.
Is controlled. Therefore, the LCD unit 1 shown in FIG.
Registers 6-1 and 6- 6 respectively holding the line direction addresses Y ₁ and Y ₂ and the column direction addresses X ₁ and X _{2 shown} in FIG.
2, 6-3, 6-4, an upper mask controller 6-5, and a lower mask controller 6-6. The upper mask control unit 6-5 includes:
Until the output of the Y-direction counter 3-2 is Y ₁ and Y ₁ and later outputs the masked off signal when the output is and X ₂ and later until the X ₁ in the X-direction counter 3-1 above mask 7-1 I do.
The lower mask control unit 6-6 receives the output of the Y-direction counter 3-2.
Time until the Y ₂ output of the X-direction counter 3-1 up and X ₂ and later becomes X _1, and Y outputs of the direction counter 3-2 Y ₂ and later under the mask of the mask off signal when the 7- Output to 2.

The mask section 7 is provided in the inclined area 1 'of the LCD section 10 shown in FIG.
It outputs 0 by masking the data of the display memory 1 so as not to be written in the other parts, and includes an upper mask 7-1 and a lower mask 7-2. The upper mask 7-1 is turned off when a mask-off signal is applied from the upper mask controller 6-5 of the mask controller 6, and the lower mask 7-2 is applied with a mask-off signal from the lower mask controller 6-6. It turns off when it is done.

The liquid crystal display control unit 8 stores the LCD unit 1 from the display memory 1.
0 when the posting data, and outputs the data shift register clock XSCL, the data line latch clock YSCL, the scanning start signal D _iN the LCD unit 10. First, data is shifted by 8 bits by the data shift register clock XSCL. When input data for one horizontal scanning direction is set in the data shift register, the data line latch clock is output.
YSCL is output, latched, and the next data in one horizontal scanning direction is input again by XSCL. Such a sequence is repeated, and when data for one frame is input, _DiN is input at the beginning of the next frame.

The CRT control section 11 performs processing control for displaying data on a CRT-screen, and outputs a horizontal synchronization signal HSYNC, a vertical synchronization signal VSYNC, a clock CLK, video data VDO, and the like. The clock CLK is also used for writing the video data VDO to the display memory 1 and also for the address counter for reading.

The synchronization circuit 12 sends a control signal to the address output unit 2-2, sends a shift clock to the VD shift register 13, and controls a data latch 14 based on the horizontal synchronization signal HSYNC and the vertical synchronization signal. Send a signal.

The VD shift register 13 sequentially receives video data output from the CRT control unit 11.

The data latch 14 temporarily holds the video data transmitted from the VD shift register 13 and sequentially sends the video data to the display memory 1.

The mode setting unit 15 outputs a control signal according to a write mode for writing data in the display memory 1 or a read mode for reading data from the display memory 1 and transferring the data to the LCD unit 10. For example, in the case of the write mode, the multiplexer 5 is connected to the address output unit 2.
-2 is output, and the read / write control unit 2-1 first outputs the write enable signal WE to the first half memory 1-1 of the display memory 1, and data is written into this. Then, a write enable signal WE is output to the latter half memory 1-2. In the case of the read mode, the multiplexer 5 controls the output of the address signal from the address conversion unit 4, operates the address control unit 3, operates the mask control unit 6, operates the liquid crystal display control unit. 8 is controlled. In addition, it controls whether the output of the display memory 1 is latched to the upper data latch 16 or the lower data latch 17.

The upper data latch 16 is the first half memory 1-1 of the display memory 1.
The output data is sequentially latched.

The lower data latch 17 is the second half memory 1-2 of the display memory 1.
The output data is sequentially latched.

 Next, the operation of FIG. 2 will be described.

(1) When writing data to the display memory, the column direction address counter 2-3 of the address output section 2-2 is cleared in synchronization with the horizontal synchronization signal HSYNC output from the CRT control section 11, and the vertical synchronization signal is written. Initialize line address counter 2-4 by VSYNC (first half memory 1
(For example, zero). When the number of display dots in the horizontal direction of the display memory 1, for example, 960 dots, is counted, it is not counted any further. When the horizontal synchronizing signal HSYNC is input, the line address counter 2-4 is counted up and the column direction address counter 2-3 is cleared. At this time, the read / write control unit 2-1 outputs a write enable signal WE to the first half memory 1-1 of the display memory 1, and the multiplexer 5 is controlled to output an address signal from the address output unit 2-2. Therefore, the video data via the VD shift register 13 and the data latch 14 is sequentially stored in the first half memory 1-
Entered in 1. And the line address counter 2-
4 counts the number of lines in the first half memory 1-1 (second half memory 1-2), and then returns to the initial setting value. After the video data has been written in the first half memory 1-1 in this way, the read / write control unit 2-1 next executes the second half memory 1--1.
2 to output a write enable signal WE. The address output unit 2-2 outputs the same address as that of the first half memory 1-1 under the same control, so that the second half memory 1-1
2 is filled with video data.

Thus, the video data write operation is repeated.

(2) When a read mode signal R is input to the mode setting unit 15 from a control unit (not shown) at the time of reading data from the display memory and writing data to the LCD unit, the video written in the display memory 1 The data is read and transcribed to the LCD unit 10,
This will be displayed on the CD device.

The multiplexer 5 outputs the address signal transmitted from the address conversion unit 4 to the display memory 1, and the address control unit 3 is operated.

In the address control unit 3, the X-direction counter 3-1 and the Y-direction counter 3-2 are cleared, and then the X-direction counter 3-1 counts up based on the clock CLK. When the X-direction counter 3-1 counts the number of horizontal dots of the LCD unit 10 (for example, 1024), the Y-direction counter 3-2 counts up by one, and the X-direction counter 3-1 returns to the initial value of zero again. It returns and performs a count operation similarly. (The upper memory 1-1 and the lower memory 1-2 are read simultaneously.) By the way, as shown in the right drawing of FIG. 3, the video data written in the display memory 1 is displayed in the hatched area 1 'of the LCD unit 10. to order, X-direction counter 3-1 in the region of 0 to X ₁ does not perform the read display memory 1. In the areas X _{2 to} Xn, the display memory 1 is read, but data is controlled to be turned off by the mask unit 7. Also, the counter 3-2 in the Y direction is 0 to 0.
Data is controlled to be turned off by the mask unit 7 in the area of Y ₁ , Y _{2 to} 2Ym.

Therefore, when the X-direction counter 3-1 and the Y-direction counter 3-2 indicate A ₁ (X ₁ , Y ₁ ), the address conversion is performed by the address conversion unit 4 so that the display memory 1 is read. Therefore, checking the count value of the X-direction counter 3-1 and Y-direction counter 3-2 operates the counters in the X direction converting unit 4-1 when it is above X _1, when became Y ₁ Y The counter of the direction converter 4-2 is operated. When the converted address is output from this, the address conversion unit 4 sends these address signals to the multiplexer 5. As a result, the first half memory 1-1 of the display memory 1,
Data is simultaneously read from the second half memory 1-2 and temporarily stored in the upper data latch 16 and the lower data latch 17, respectively.

By the way, the mask control section 6 controls the data not to be written in the area of the LCD section 10 other than the hatched area 1 'in FIG. 3, as described above. A control unit 6-6;
The upper mask 7-1 and the lower mask 7-2 are controlled on the basis of the data written in -1 to 6-4 so that the upper mask 7-1 and the lower mask 7-1 are addressed when the shaded area 1 'is addressed.
Then, the lower mask 7-2 is turned on to transfer the data.

Since data is transferred to the LCD unit 10 in units of 8 bits, 8 bits of data are read from the display memory 1 and, as described above, 1 bit is read by the data shift register clock XSCL.
Data is set in the horizontal direction and latched by the data line latch clock YSCL. And one frame
When the transfer control to the LCD unit 10 is completed, the scan start signal _DiN
Is output, and control for the next frame is performed.

In the above description, an example in which the display memory 1 and the LCD unit 10 are each divided into two has been described. However, the present invention is not limited to this.
Even in the case where the number of screens is divided into three or more, the same control can be performed with the same number of screens constituting the display memory and the LCD unit. Instead of using a mask separately, a mask function may be added to the upper data latch and the lower data latch, and a fixed value of zero may be output to areas other than the hatched area 1 '.

〔The invention's effect〕

As described above, according to the present invention, even when the dot size of the display memory on the main body side and the dot size of the LCD device are different, display on the LCD device is possible, so that the same LCD device can be used for a plurality of types of main body devices. It can be used.

[Brief description of the drawings]

 FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is an explanatory diagram of an operation state of the present invention, and FIG. 1 Display memory 2 Memory control unit 3 Address control unit 4 Address conversion unit 5 Multiplexer 6 Mask control unit 7 Mask unit 8 Liquid crystal display control unit 10 LCD unit

Claims (1)

(57) [Claims] 1. A display data memory means (1) and a memory control means (2), wherein data written in the display data memory means (2) by the memory control means is transferred to a liquid crystal display (10). A liquid crystal display control device for displaying, comprising: an address output means (3) for outputting an address corresponding to a displayable area of a liquid crystal display (10); and an address in an x direction and a y direction output by the address output means (3). Address conversion means (4) for converting signals into x- and y-direction addresses corresponding to the memory areas of the display data memory means (1); and mask control means (6). ) Is transferred to the liquid crystal display means (10), the display data memory means (1) is read by the output signal of the address conversion means (4). A liquid crystal display device characterized in that a region not transcribed to the liquid crystal display means (10) is controlled by the mask control means (6) so as not to write data.